spl.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/mach-imx/iomux-v3.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx8mm_pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/mach-imx/boot_mode.h>
  13. #include <asm/arch/ddr.h>
  14. #include <dm/uclass.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass-internal.h>
  17. #include <dm/device-internal.h>
  18. #include <power/pmic.h>
  19. #include <power/bd71837.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int spl_board_boot_device(enum boot_device boot_dev_spl)
  22. {
  23. switch (boot_dev_spl) {
  24. case SD2_BOOT:
  25. case MMC2_BOOT:
  26. return BOOT_DEVICE_MMC1;
  27. case SD3_BOOT:
  28. case MMC3_BOOT:
  29. return BOOT_DEVICE_MMC2;
  30. default:
  31. return BOOT_DEVICE_NONE;
  32. }
  33. }
  34. void spl_dram_init(void)
  35. {
  36. ddr_init(&dram_timing);
  37. }
  38. void spl_board_init(void)
  39. {
  40. puts("Normal Boot\n");
  41. }
  42. #ifdef CONFIG_SPL_LOAD_FIT
  43. int board_fit_config_name_match(const char *name)
  44. {
  45. /* Just empty function now - can't decide what to choose */
  46. debug("%s: %s\n", __func__, name);
  47. return 0;
  48. }
  49. #endif
  50. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  51. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  52. static iomux_v3_cfg_t const uart_pads[] = {
  53. IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  54. IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  55. };
  56. static iomux_v3_cfg_t const wdog_pads[] = {
  57. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  58. };
  59. int board_early_init_f(void)
  60. {
  61. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  62. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  63. set_wdog_reset(wdog);
  64. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  65. return 0;
  66. }
  67. int power_init_board(void)
  68. {
  69. struct udevice *dev;
  70. int ret;
  71. ret = pmic_get("pmic@4b", &dev);
  72. if (ret == -ENODEV) {
  73. puts("No pmic\n");
  74. return 0;
  75. }
  76. if (ret != 0)
  77. return ret;
  78. /* decrease RESET key long push time from the default 10s to 10ms */
  79. pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
  80. /* unlock the PMIC regs */
  81. pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
  82. /* increase VDD_SOC to typical value 0.85v before first DRAM access */
  83. pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
  84. /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
  85. pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
  86. #ifndef CONFIG_IMX8M_LPDDR4
  87. /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  88. pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
  89. #endif
  90. /* lock the PMIC regs */
  91. pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
  92. return 0;
  93. }
  94. void board_init_f(ulong dummy)
  95. {
  96. struct udevice *dev;
  97. int ret;
  98. arch_cpu_init();
  99. init_uart_clk(1);
  100. board_early_init_f();
  101. timer_init();
  102. preloader_console_init();
  103. /* Clear the BSS. */
  104. memset(__bss_start, 0, __bss_end - __bss_start);
  105. ret = spl_early_init();
  106. if (ret) {
  107. debug("spl_early_init() failed: %d\n", ret);
  108. hang();
  109. }
  110. ret = uclass_get_device_by_name(UCLASS_CLK,
  111. "clock-controller@30380000",
  112. &dev);
  113. if (ret < 0) {
  114. printf("Failed to find clock node. Check device tree\n");
  115. hang();
  116. }
  117. enable_tzc380();
  118. power_init_board();
  119. /* DDR initialization */
  120. spl_dram_init();
  121. board_init_r(NULL, 0);
  122. }
  123. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  124. {
  125. puts ("resetting ...\n");
  126. reset_cpu(WDOG1_BASE_ADDR);
  127. return 0;
  128. }