eth_hydra.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Author: Timur Tabi <timur@freescale.com>
  5. */
  6. /*
  7. * This file handles the board muxing between the Fman Ethernet MACs and
  8. * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
  9. * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
  10. * provided by the standard Freescale four-port SGMII riser card. The 10Gb
  11. * XGMII PHY is provided via the XAUI riser card. Since there is only one
  12. * Fman device on a P3041 and P5020, we only support one SGMII card and one
  13. * RGMII card.
  14. *
  15. * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
  16. * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
  17. * always the same (0). The value for SGMII depends on which slot the riser is
  18. * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
  19. * the value is based on which slot the XAUI is inserted in.
  20. *
  21. * The SERDES configuration is used to determine where the SGMII and XAUI cards
  22. * exist, and also which Fman MACs are routed to which PHYs. So for a given
  23. * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
  24. * to PHYs dynamically.
  25. *
  26. *
  27. * This file also updates the device tree in three ways:
  28. *
  29. * 1) The status of each virtual MDIO node that is referenced by an Ethernet
  30. * node is set to "okay".
  31. *
  32. * 2) The phy-handle property of each active Ethernet MAC node is set to the
  33. * appropriate PHY node.
  34. *
  35. * 3) The "mux value" for each virtual MDIO node is set to the correct value,
  36. * if necessary. Some virtual MDIO nodes do not have configurable mux
  37. * values, so those values are hard-coded in the DTS. On the HYDRA board,
  38. * the virtual MDIO node for the SGMII card needs to be updated.
  39. *
  40. * For all this to work, the device tree needs to have the following:
  41. *
  42. * 1) An alias for each PHY node that an Ethernet node could be routed to.
  43. *
  44. * 2) An alias for each real and virtual MDIO node that is disabled by default
  45. * and might need to be enabled, and also might need to have its mux-value
  46. * updated.
  47. */
  48. #include <common.h>
  49. #include <netdev.h>
  50. #include <asm/fsl_serdes.h>
  51. #include <fm_eth.h>
  52. #include <fsl_mdio.h>
  53. #include <malloc.h>
  54. #include <fdt_support.h>
  55. #include <fsl_dtsec.h>
  56. #include "../common/ngpixis.h"
  57. #include "../common/fman.h"
  58. #ifdef CONFIG_FMAN_ENET
  59. #define BRDCFG1_EMI1_SEL_MASK 0x78
  60. #define BRDCFG1_EMI1_SEL_SLOT1 0x10
  61. #define BRDCFG1_EMI1_SEL_SLOT2 0x20
  62. #define BRDCFG1_EMI1_SEL_SLOT5 0x30
  63. #define BRDCFG1_EMI1_SEL_SLOT6 0x40
  64. #define BRDCFG1_EMI1_SEL_SLOT7 0x50
  65. #define BRDCFG1_EMI1_SEL_RGMII 0x00
  66. #define BRDCFG1_EMI1_EN 0x08
  67. #define BRDCFG1_EMI2_SEL_MASK 0x06
  68. #define BRDCFG1_EMI2_SEL_SLOT1 0x00
  69. #define BRDCFG1_EMI2_SEL_SLOT2 0x02
  70. #define BRDCFG2_REG_GPIO_SEL 0x20
  71. #define PHY_BASE_ADDR 0x00
  72. /*
  73. * BRDCFG1 mask and value for each MAC
  74. *
  75. * This array contains the BRDCFG1 values (in mask/val format) that route the
  76. * MDIO bus to a particular RGMII or SGMII PHY.
  77. */
  78. struct {
  79. u8 mask;
  80. u8 val;
  81. } mdio_mux[NUM_FM_PORTS];
  82. /*
  83. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  84. * that the mapping must be determined dynamically, or that the lane maps to
  85. * something other than a board slot
  86. */
  87. static u8 lane_to_slot[] = {
  88. 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
  89. };
  90. /*
  91. * Set the board muxing for a given MAC
  92. *
  93. * The MDIO layer calls this function every time it wants to talk to a PHY.
  94. */
  95. void hydra_mux_mdio(u8 mask, u8 val)
  96. {
  97. clrsetbits_8(&pixis->brdcfg1, mask, val);
  98. }
  99. struct hydra_mdio {
  100. u8 mask;
  101. u8 val;
  102. struct mii_dev *realbus;
  103. };
  104. static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
  105. int regnum)
  106. {
  107. struct hydra_mdio *priv = bus->priv;
  108. hydra_mux_mdio(priv->mask, priv->val);
  109. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  110. }
  111. static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
  112. int regnum, u16 value)
  113. {
  114. struct hydra_mdio *priv = bus->priv;
  115. hydra_mux_mdio(priv->mask, priv->val);
  116. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  117. }
  118. static int hydra_mdio_reset(struct mii_dev *bus)
  119. {
  120. struct hydra_mdio *priv = bus->priv;
  121. return priv->realbus->reset(priv->realbus);
  122. }
  123. static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
  124. {
  125. struct mii_dev *bus = miiphy_get_dev_by_name(name);
  126. struct hydra_mdio *priv = bus->priv;
  127. priv->mask = mask;
  128. priv->val = val;
  129. }
  130. static int hydra_mdio_init(char *realbusname, char *fakebusname)
  131. {
  132. struct hydra_mdio *hmdio;
  133. struct mii_dev *bus = mdio_alloc();
  134. if (!bus) {
  135. printf("Failed to allocate Hydra MDIO bus\n");
  136. return -1;
  137. }
  138. hmdio = malloc(sizeof(*hmdio));
  139. if (!hmdio) {
  140. printf("Failed to allocate Hydra private data\n");
  141. free(bus);
  142. return -1;
  143. }
  144. bus->read = hydra_mdio_read;
  145. bus->write = hydra_mdio_write;
  146. bus->reset = hydra_mdio_reset;
  147. strcpy(bus->name, fakebusname);
  148. hmdio->realbus = miiphy_get_dev_by_name(realbusname);
  149. if (!hmdio->realbus) {
  150. printf("No bus with name %s\n", realbusname);
  151. free(bus);
  152. free(hmdio);
  153. return -1;
  154. }
  155. bus->priv = hmdio;
  156. return mdio_register(bus);
  157. }
  158. /*
  159. * Given an alias or a path for a node, set the mux value of that node.
  160. *
  161. * If 'alias' is not a valid alias, then it is treated as a full path to the
  162. * node. No error checking is performed.
  163. *
  164. * This function is normally called to set the fsl,hydra-mdio-muxval property
  165. * of a virtual MDIO node.
  166. */
  167. static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
  168. {
  169. const char *path = fdt_get_alias(fdt, alias);
  170. if (!path)
  171. path = alias;
  172. do_fixup_by_path(fdt, path, "reg",
  173. &mux, sizeof(mux), 1);
  174. do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
  175. &mux, sizeof(mux), 1);
  176. }
  177. /*
  178. * Given the following ...
  179. *
  180. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  181. * compatible string and 'addr' physical address)
  182. *
  183. * 2) An Fman port
  184. *
  185. * ... update the phy-handle property of the Ethernet node to point to the
  186. * right PHY. This assumes that we already know the PHY for each port. That
  187. * information is stored in mdio_mux[].
  188. *
  189. * The offset of the Fman Ethernet node is also passed in for convenience, but
  190. * it is not used, and we recalculate the offset anyway.
  191. *
  192. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  193. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  194. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  195. * and ports are the same thing.
  196. *
  197. * Note that this code would be cleaner if had a function called
  198. * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
  199. * array. That's because all we're doing is figuring out the PHY address for
  200. * a given Fman MAC and writing it to the device tree. Well, we already did
  201. * the hard work to figure that out in board_eth_init(), so it's silly to
  202. * repeat that here.
  203. */
  204. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  205. enum fm_port port, int offset)
  206. {
  207. unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
  208. char phy[16];
  209. if (port == FM1_10GEC1) {
  210. /* XAUI */
  211. int lane = serdes_get_first_lane(XAUI_FM1);
  212. if (lane >= 0) {
  213. /* The XAUI PHY is identified by the slot */
  214. sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
  215. fdt_set_phy_handle(fdt, compat, addr, phy);
  216. }
  217. return;
  218. }
  219. if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
  220. /* RGMII */
  221. /* The RGMII PHY is identified by the MAC connected to it */
  222. sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
  223. fdt_set_phy_handle(fdt, compat, addr, phy);
  224. return;
  225. }
  226. /* If it's not RGMII or XGMII, it must be SGMII */
  227. if (mux) {
  228. /* The SGMII PHY is identified by the MAC connected to it */
  229. sprintf(phy, "phy_sgmii_%x",
  230. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
  231. fdt_set_phy_handle(fdt, compat, addr, phy);
  232. }
  233. }
  234. #define PIXIS_SW2_LANE_23_SEL 0x80
  235. #define PIXIS_SW2_LANE_45_SEL 0x40
  236. #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
  237. #define PIXIS_SW2_LANE_67_SEL_5 0x00
  238. #define PIXIS_SW2_LANE_67_SEL_6 0x20
  239. #define PIXIS_SW2_LANE_67_SEL_7 0x10
  240. #define PIXIS_SW2_LANE_8_SEL 0x08
  241. #define PIXIS_SW2_LANE_1617_SEL 0x04
  242. /*
  243. * Initialize the lane_to_slot[] array.
  244. *
  245. * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
  246. * slots is hard-coded. On the Hydra board, however, the mapping is controlled
  247. * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
  248. * initialized.
  249. */
  250. static void initialize_lane_to_slot(void)
  251. {
  252. u8 sw2 = in_8(&PIXIS_SW(2));
  253. lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
  254. lane_to_slot[3] = lane_to_slot[2];
  255. lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
  256. lane_to_slot[5] = lane_to_slot[4];
  257. switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
  258. case PIXIS_SW2_LANE_67_SEL_5:
  259. lane_to_slot[6] = 5;
  260. break;
  261. case PIXIS_SW2_LANE_67_SEL_6:
  262. lane_to_slot[6] = 6;
  263. break;
  264. case PIXIS_SW2_LANE_67_SEL_7:
  265. lane_to_slot[6] = 7;
  266. break;
  267. }
  268. lane_to_slot[7] = lane_to_slot[6];
  269. lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
  270. lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
  271. lane_to_slot[17] = lane_to_slot[16];
  272. }
  273. #endif /* #ifdef CONFIG_FMAN_ENET */
  274. /*
  275. * Configure the status for the virtual MDIO nodes
  276. *
  277. * Rather than create the virtual MDIO nodes from scratch for each active
  278. * virtual MDIO, we expect the DTS to have the nodes defined already, and we
  279. * only enable the ones that are actually active.
  280. *
  281. * We assume that the DTS already hard-codes the status for all the
  282. * virtual MDIO nodes to "disabled", so all we need to do is enable the
  283. * active ones.
  284. *
  285. * For SGMII, we also need to set the mux value in the node.
  286. */
  287. void fdt_fixup_board_enet(void *fdt)
  288. {
  289. #ifdef CONFIG_FMAN_ENET
  290. unsigned int i;
  291. int lane;
  292. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  293. int idx = i - FM1_DTSEC1;
  294. switch (fm_info_get_enet_if(i)) {
  295. case PHY_INTERFACE_MODE_SGMII:
  296. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  297. if (lane >= 0) {
  298. fdt_status_okay_by_alias(fdt, "emi1_sgmii");
  299. /* Also set the MUX value */
  300. fdt_set_mdio_mux(fdt, "emi1_sgmii",
  301. mdio_mux[i].val);
  302. }
  303. break;
  304. case PHY_INTERFACE_MODE_RGMII:
  305. fdt_status_okay_by_alias(fdt, "emi1_rgmii");
  306. break;
  307. default:
  308. break;
  309. }
  310. }
  311. lane = serdes_get_first_lane(XAUI_FM1);
  312. if (lane >= 0)
  313. fdt_status_okay_by_alias(fdt, "emi2_xgmii");
  314. #endif
  315. }
  316. int board_eth_init(bd_t *bis)
  317. {
  318. #ifdef CONFIG_FMAN_ENET
  319. struct fsl_pq_mdio_info dtsec_mdio_info;
  320. struct tgec_mdio_info tgec_mdio_info;
  321. unsigned int i, slot;
  322. int lane;
  323. struct mii_dev *bus;
  324. printf("Initializing Fman\n");
  325. initialize_lane_to_slot();
  326. /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
  327. setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
  328. memset(mdio_mux, 0, sizeof(mdio_mux));
  329. dtsec_mdio_info.regs =
  330. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  331. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  332. /* Register the real 1G MDIO bus */
  333. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  334. tgec_mdio_info.regs =
  335. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  336. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  337. /* Register the real 10G MDIO bus */
  338. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  339. /* Register the three virtual MDIO front-ends */
  340. hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
  341. hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
  342. /*
  343. * Program the DTSEC PHY addresses assuming that they are all SGMII.
  344. * For any DTSEC that's RGMII, we'll override its PHY address later.
  345. * We assume that DTSEC5 is only used for RGMII.
  346. */
  347. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  348. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  349. fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  350. fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  351. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  352. int idx = i - FM1_DTSEC1;
  353. switch (fm_info_get_enet_if(i)) {
  354. case PHY_INTERFACE_MODE_SGMII:
  355. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  356. if (lane < 0)
  357. break;
  358. slot = lane_to_slot[lane];
  359. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  360. switch (slot) {
  361. case 1:
  362. /* Always DTSEC5 on Bank 3 */
  363. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  364. BRDCFG1_EMI1_EN;
  365. break;
  366. case 2:
  367. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  368. BRDCFG1_EMI1_EN;
  369. break;
  370. case 5:
  371. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  372. BRDCFG1_EMI1_EN;
  373. break;
  374. case 6:
  375. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  376. BRDCFG1_EMI1_EN;
  377. break;
  378. case 7:
  379. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  380. BRDCFG1_EMI1_EN;
  381. break;
  382. };
  383. hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
  384. mdio_mux[i].mask, mdio_mux[i].val);
  385. fm_info_set_mdio(i,
  386. miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
  387. break;
  388. case PHY_INTERFACE_MODE_RGMII:
  389. /*
  390. * If DTSEC4 is RGMII, then it's routed via via EC1 to
  391. * the first on-board RGMII port. If DTSEC5 is RGMII,
  392. * then it's routed via via EC2 to the second on-board
  393. * RGMII port. The other DTSECs cannot be routed to
  394. * RGMII.
  395. */
  396. fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
  397. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  398. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  399. BRDCFG1_EMI1_EN;
  400. hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
  401. mdio_mux[i].mask, mdio_mux[i].val);
  402. fm_info_set_mdio(i,
  403. miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
  404. break;
  405. case PHY_INTERFACE_MODE_NONE:
  406. fm_info_set_phy_address(i, 0);
  407. break;
  408. default:
  409. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  410. idx + 1, fm_info_get_enet_if(i));
  411. fm_info_set_phy_address(i, 0);
  412. break;
  413. }
  414. }
  415. bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
  416. set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
  417. /*
  418. * For 10G, we only support one XAUI card per Fman. If present, then we
  419. * force its routing and never touch those bits again, which removes the
  420. * need for Linux to do any muxing. This works because of the way
  421. * BRDCFG1 is defined, but it's a bit hackish.
  422. *
  423. * The PHY address for the XAUI card depends on which slot it's in. The
  424. * macros we use imply that the PHY address is based on which FM, but
  425. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  426. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  427. * check the actual slot and just use the macros as-is, even though
  428. * the P3041 and P5020 only have one Fman.
  429. */
  430. lane = serdes_get_first_lane(XAUI_FM1);
  431. if (lane >= 0) {
  432. slot = lane_to_slot[lane];
  433. if (slot == 1) {
  434. /* XAUI card is in slot 1 */
  435. clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
  436. BRDCFG1_EMI2_SEL_SLOT1);
  437. fm_info_set_phy_address(FM1_10GEC1,
  438. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  439. } else {
  440. /* XAUI card is in slot 2 */
  441. clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
  442. BRDCFG1_EMI2_SEL_SLOT2);
  443. fm_info_set_phy_address(FM1_10GEC1,
  444. CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
  445. }
  446. }
  447. fm_info_set_mdio(FM1_10GEC1,
  448. miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
  449. cpu_eth_init(bis);
  450. #endif
  451. return pci_eth_init(bis);
  452. }