corenet_ds.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <netdev.h>
  10. #include <linux/compiler.h>
  11. #include <asm/mmu.h>
  12. #include <asm/processor.h>
  13. #include <asm/cache.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_law.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <fm_eth.h>
  19. #include "../common/ngpixis.h"
  20. #include "corenet_ds.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int checkboard (void)
  23. {
  24. u8 sw;
  25. struct cpu_type *cpu = gd->arch.cpu;
  26. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  27. defined(CONFIG_TARGET_P5040DS)
  28. unsigned int i;
  29. #endif
  30. static const char * const freq[] = {"100", "125", "156.25", "212.5" };
  31. printf("Board: %sDS, ", cpu->name);
  32. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  33. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  34. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  35. sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  36. if (sw < 0x8)
  37. printf("vBank: %d\n", sw);
  38. else if (sw == 0x8)
  39. puts("Promjet\n");
  40. else if (sw == 0x9)
  41. puts("NAND\n");
  42. else
  43. printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
  44. /* Display the actual SERDES reference clocks as configured by the
  45. * dip switches on the board. Note that the SWx registers could
  46. * technically be set to force the reference clocks to match the
  47. * values that the SERDES expects (or vice versa). For now, however,
  48. * we just display both values and hope the user notices when they
  49. * don't match.
  50. */
  51. puts("SERDES Reference Clocks: ");
  52. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  53. defined(CONFIG_TARGET_P5040DS)
  54. sw = in_8(&PIXIS_SW(5));
  55. for (i = 0; i < 3; i++) {
  56. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  57. printf("Bank%u=%sMhz ", i+1, freq[clock]);
  58. }
  59. #ifdef CONFIG_TARGET_P5040DS
  60. /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
  61. sw = in_8(&PIXIS_SW(9));
  62. printf("Bank4=%sMhz ", freq[sw & 3]);
  63. #endif
  64. puts("\n");
  65. #else
  66. sw = in_8(&PIXIS_SW(3));
  67. /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
  68. /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
  69. /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
  70. printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
  71. printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
  72. printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
  73. #endif
  74. return 0;
  75. }
  76. int board_early_init_f(void)
  77. {
  78. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  79. /*
  80. * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
  81. * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  82. * the noise introduced by these unterminated and unused clock pairs.
  83. */
  84. setbits_be32(&gur->ddrclkdr, 0x001B001B);
  85. return 0;
  86. }
  87. int board_early_init_r(void)
  88. {
  89. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  90. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  91. /*
  92. * Remap Boot flash + PROMJET region to caching-inhibited
  93. * so that flash can be erased properly.
  94. */
  95. /* Flush d-cache and invalidate i-cache of any FLASH data */
  96. flush_dcache();
  97. invalidate_icache();
  98. if (flash_esel == -1) {
  99. /* very unlikely unless something is messed up */
  100. puts("Error: Could not find TLB for FLASH BASE\n");
  101. flash_esel = 2; /* give our best effort to continue */
  102. } else {
  103. /* invalidate existing TLB entry for flash + promjet */
  104. disable_tlb(flash_esel);
  105. }
  106. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  107. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  108. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  109. return 0;
  110. }
  111. #define NUM_SRDS_BANKS 3
  112. int misc_init_r(void)
  113. {
  114. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  115. u32 actual[NUM_SRDS_BANKS];
  116. unsigned int i;
  117. u8 sw;
  118. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  119. defined(CONFIG_TARGET_P5040DS)
  120. sw = in_8(&PIXIS_SW(5));
  121. for (i = 0; i < 3; i++) {
  122. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  123. switch (clock) {
  124. case 0:
  125. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  126. break;
  127. case 1:
  128. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  129. break;
  130. case 2:
  131. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  132. break;
  133. default:
  134. printf("Warning: SDREFCLK%u switch setting of '11' is "
  135. "unsupported\n", i + 1);
  136. break;
  137. }
  138. }
  139. #else
  140. /* Warn if the expected SERDES reference clocks don't match the
  141. * actual reference clocks. This needs to be done after calling
  142. * p4080_erratum_serdes8(), since that function may modify the clocks.
  143. */
  144. sw = in_8(&PIXIS_SW(3));
  145. actual[0] = (sw & 0x40) ?
  146. SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
  147. actual[1] = (sw & 0x20) ?
  148. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  149. actual[2] = (sw & 0x10) ?
  150. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  151. #endif
  152. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  153. u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  154. if (expected != actual[i]) {
  155. printf("Warning: SERDES bank %u expects reference clock"
  156. " %sMHz, but actual is %sMHz\n", i + 1,
  157. serdes_clock_to_string(expected),
  158. serdes_clock_to_string(actual[i]));
  159. }
  160. }
  161. return 0;
  162. }
  163. int ft_board_setup(void *blob, bd_t *bd)
  164. {
  165. phys_addr_t base;
  166. phys_size_t size;
  167. ft_cpu_setup(blob, bd);
  168. base = env_get_bootm_low();
  169. size = env_get_bootm_size();
  170. fdt_fixup_memory(blob, (u64)base, (u64)size);
  171. #ifdef CONFIG_PCI
  172. pci_of_setup(blob, bd);
  173. #endif
  174. fdt_fixup_liodn(blob);
  175. fsl_fdt_fixup_dr_usb(blob, bd);
  176. #ifdef CONFIG_SYS_DPAA_FMAN
  177. fdt_fixup_fman_ethernet(blob);
  178. fdt_fixup_board_enet(blob);
  179. #endif
  180. return 0;
  181. }