README 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151
  1. Overview
  2. --------
  3. - BSC9131 is integrated device that targets Femto base station market.
  4. It combines Power Architecture e500v2 and DSP StarCore SC3850 core
  5. technologies with MAPLE-B2F baseband acceleration processing elements.
  6. - It's MAPLE disabled personality is called 9231.
  7. The BSC9131 SoC includes the following function and features:
  8. . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
  9. L2 cache
  10. . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
  11. . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  12. Processing (MAPLE-B2F)
  13. . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
  14. Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
  15. and CRC algorithms
  16. . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
  17. Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
  18. operations
  19. . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
  20. ECC, up to 400-MHz clock/800 MHz data rate
  21. . Dedicated security engine featuring trusted boot
  22. . DMA controller
  23. . OCNDMA with four bidirectional channels
  24. . Interfaces
  25. . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
  26. including IEEE 1588. v2 hardware support and virtualization (eTSEC)
  27. . eTSEC 1 supports RGMII/RMII
  28. . eTSEC 2 supports RGMII
  29. . High-speed USB 2.0 host and device controller with ULPI interface
  30. . Enhanced secure digital (SD/MMC) host controller (eSDHC)
  31. . Antenna interface controller (AIC), supporting three industry standard
  32. JESD207/three custom ADI RF interfaces (two dual port and one single port)
  33. and three MAXIM's MaxPHY serial interfaces
  34. . ADI lanes support both full duplex FDD support and half duplex TDD support
  35. . Universal Subscriber Identity Module (USIM) interface that facilitates
  36. communication to SIM cards or Eurochip pre-paid phone cards
  37. . TDM with one TDM port
  38. . Two DUART, four eSPI, and two I2C controllers
  39. . Integrated Flash memory controller (IFC)
  40. . TDM with 256 channels
  41. . GPIO
  42. . Sixteen 32-bit timers
  43. The e500 core subsystem within the Power Architecture consists of the following:
  44. . 32-Kbyte L1 instruction cache
  45. . 32-Kbyte L1 data cache
  46. . 256-Kbyte L2 cache/L2 memory/L2 stash
  47. . programmable interrupt controller (PIC)
  48. . Debug support
  49. . Timers
  50. The SC3850 core subsystem consists of the following:
  51. . 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
  52. . 32 Kbyte 8-way level 1 data cache (L1 DCache)
  53. . 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
  54. . Memory management unit (MMU)
  55. . Enhanced programmable interrupt controller (EPIC)
  56. . Debug and profiling unit (DPU)
  57. . Two 32-bit timers
  58. BSC9131RDB board Overview
  59. -------------------------
  60. 1Gbyte DDR3 (on board DDR)
  61. 128Mbyte 2K page size NAND Flash
  62. 256 Kbit M24256 I2C EEPROM
  63. 128 Mbit SPI Flash memory
  64. USB-ULPI
  65. eTSEC1: Connected to RGMII PHY
  66. eTSEC2: Connected to RGMII PHY
  67. DUART interface: supports one UARTs up to 115200 bps for console display
  68. USIM connector
  69. Frequency Combinations Supported
  70. --------------------------------
  71. Core MHz/CCB MHz/DDR(MT/s)
  72. 1. 1000/500/800
  73. 2. 800/400/667
  74. Boot Methods Supported
  75. -----------------------
  76. 1. NAND Flash
  77. 2. SPI Flash
  78. Default Boot Method
  79. --------------------
  80. NAND boot
  81. Building U-Boot
  82. --------------
  83. To build the U-Boot for BSC9131RDB:
  84. 1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
  85. make BSC9131RDB_NAND
  86. 2. NAND Flash with sysclk 100MHz(J16 on RDB open)
  87. make BSC9131RDB_NAND_SYSCLK100
  88. 3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
  89. make BSC9131RDB_SPIFLASH
  90. 4. SPI Flash with sysclk 100MHz(J16 on RDB open)
  91. make BSC9131RDB_SPIFLASH_SYSCLK100
  92. Memory map
  93. -----------
  94. 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
  95. 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
  96. 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
  97. 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
  98. 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
  99. 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
  100. 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
  101. 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
  102. 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
  103. 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
  104. DDR Memory map
  105. ---------------
  106. 0x0000_0000 0x36FF_FFFF Memory passed onto Linux
  107. 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
  108. 0x3800_0000 0x4FFF_FFFF DSP Private area
  109. Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
  110. data communcation between PowerPC and DSP core.
  111. Rest is PowerPC private area.
  112. Flashing Images
  113. ---------------
  114. To place a new U-Boot image in the NAND flash and then boot
  115. with that new image temporarily, use this:
  116. tftp 1000000 u-boot-nand.bin
  117. nand erase 0 100000
  118. nand write 1000000 0 100000
  119. reset
  120. Using the Device Tree Source File
  121. ---------------------------------
  122. To create the DTB (Device Tree Binary) image file,
  123. use a command similar to this:
  124. dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
  125. Likely, that .dts file will come from here;
  126. linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
  127. Booting Linux
  128. -------------
  129. Place a linux uImage in the TFTP disk area.
  130. tftp 1000000 uImage
  131. tftp 2000000 rootfs.ext2.gz.uboot
  132. tftp c00000 bsc9131rdb.dtb
  133. bootm 1000000 2000000 c00000