vme8349.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * vme8349.c -- esd VME8349 board support
  4. *
  5. * Copyright (c) 2008-2009 esd gmbh.
  6. *
  7. * (C) Copyright 2006
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. *
  10. * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
  11. * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
  12. */
  13. #include <common.h>
  14. #include <ioports.h>
  15. #include <mpc83xx.h>
  16. #include <asm/mpc8349_pci.h>
  17. #if defined(CONFIG_OF_LIBFDT)
  18. #include <linux/libfdt.h>
  19. #endif
  20. #include <asm/io.h>
  21. #include <asm/mmu.h>
  22. #include <spd.h>
  23. #include <spd_sdram.h>
  24. #include <i2c.h>
  25. #include <netdev.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. void ddr_enable_ecc(unsigned int dram_size);
  28. int dram_init(void)
  29. {
  30. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  31. u32 msize = 0;
  32. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  33. return -ENXIO;
  34. /* DDR SDRAM - Main memory */
  35. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  36. msize = spd_sdram();
  37. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  38. /*
  39. * Initialize and enable DDR ECC.
  40. */
  41. ddr_enable_ecc(msize * 1024 * 1024);
  42. #endif
  43. /* Now check memory size (after ECC is initialized) */
  44. msize = get_ram_size(0, msize);
  45. /* return total bus SDRAM size(bytes) -- DDR */
  46. gd->ram_size = msize * 1024 * 1024;
  47. return 0;
  48. }
  49. int checkboard(void)
  50. {
  51. #ifdef CONFIG_TARGET_CADDY2
  52. puts("Board: esd VME-CADDY/2\n");
  53. #else
  54. puts("Board: esd VME-CPU/8349\n");
  55. #endif
  56. return 0;
  57. }
  58. #ifdef CONFIG_TARGET_CADDY2
  59. int board_eth_init(bd_t *bis)
  60. {
  61. return pci_eth_init(bis);
  62. }
  63. #endif
  64. #if defined(CONFIG_OF_BOARD_SETUP)
  65. int ft_board_setup(void *blob, bd_t *bd)
  66. {
  67. ft_cpu_setup(blob, bd);
  68. #ifdef CONFIG_PCI
  69. ft_pci_setup(blob, bd);
  70. #endif
  71. return 0;
  72. }
  73. #endif
  74. int misc_init_r()
  75. {
  76. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  77. clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
  78. return 0;
  79. }
  80. /*
  81. * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
  82. * and VME-CADDY/2) have different SDRAM configurations.
  83. */
  84. #ifdef CONFIG_TARGET_CADDY2
  85. #define SMALL_RAM 0xff
  86. #define LARGE_RAM 0x00
  87. #else
  88. #define SMALL_RAM 0x00
  89. #define LARGE_RAM 0xff
  90. #endif
  91. #define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
  92. static spd_eeprom_t default_spd_eeprom = {
  93. SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
  94. SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
  95. SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
  96. SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
  97. SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
  98. SPD_VAL(0x00, 0x00), /* 05 */
  99. SPD_VAL(0x40, 0x40), /* 06 */
  100. SPD_VAL(0x00, 0x00), /* 07 */
  101. SPD_VAL(0x05, 0x05), /* 08 */
  102. SPD_VAL(0x30, 0x30), /* 09 */
  103. SPD_VAL(0x45, 0x45), /* 10 */
  104. SPD_VAL(0x02, 0x02), /* 11 ecc used */
  105. SPD_VAL(0x82, 0x82), /* 12 */
  106. SPD_VAL(0x10, 0x10), /* 13 */
  107. SPD_VAL(0x08, 0x08), /* 14 */
  108. SPD_VAL(0x00, 0x00), /* 15 */
  109. SPD_VAL(0x0c, 0x0c), /* 16 */
  110. SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
  111. SPD_VAL(0x38, 0x38), /* 18 */
  112. SPD_VAL(0x00, 0x00), /* 19 */
  113. SPD_VAL(0x02, 0x02), /* 20 */
  114. SPD_VAL(0x00, 0x00), /* 21 */
  115. SPD_VAL(0x03, 0x03), /* 22 */
  116. SPD_VAL(0x3d, 0x3d), /* 23 */
  117. SPD_VAL(0x45, 0x45), /* 24 */
  118. SPD_VAL(0x50, 0x50), /* 25 */
  119. SPD_VAL(0x45, 0x45), /* 26 */
  120. SPD_VAL(0x3c, 0x3c), /* 27 */
  121. SPD_VAL(0x28, 0x28), /* 28 */
  122. SPD_VAL(0x3c, 0x3c), /* 29 */
  123. SPD_VAL(0x2d, 0x2d), /* 30 */
  124. SPD_VAL(0x20, 0x80), /* 31 */
  125. SPD_VAL(0x20, 0x20), /* 32 */
  126. SPD_VAL(0x27, 0x27), /* 33 */
  127. SPD_VAL(0x10, 0x10), /* 34 */
  128. SPD_VAL(0x17, 0x17), /* 35 */
  129. SPD_VAL(0x3c, 0x3c), /* 36 */
  130. SPD_VAL(0x1e, 0x1e), /* 37 */
  131. SPD_VAL(0x1e, 0x1e), /* 38 */
  132. SPD_VAL(0x00, 0x00), /* 39 */
  133. SPD_VAL(0x00, 0x06), /* 40 */
  134. SPD_VAL(0x37, 0x37), /* 41 */
  135. SPD_VAL(0x4b, 0x7f), /* 42 */
  136. SPD_VAL(0x80, 0x80), /* 43 */
  137. SPD_VAL(0x18, 0x18), /* 44 */
  138. SPD_VAL(0x22, 0x22), /* 45 */
  139. SPD_VAL(0x00, 0x00), /* 46 */
  140. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  141. SPD_VAL(0x10, 0x10), /* 62 */
  142. SPD_VAL(0x7e, 0x1d), /* 63 */
  143. { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
  144. SPD_VAL(0x00, 0x00), /* 72 */
  145. #ifdef CONFIG_TARGET_CADDY2
  146. { "vme-caddy/2 ram " }
  147. #else
  148. { "vme-cpu/2 ram " }
  149. #endif
  150. };
  151. int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
  152. {
  153. int old_bus = i2c_get_bus_num();
  154. unsigned int l, sum;
  155. int valid = 0;
  156. i2c_set_bus_num(0);
  157. if (i2c_read(chip, addr, alen, buffer, len) == 0)
  158. if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
  159. sum = 0;
  160. for (l = 0; l < 63; l++)
  161. sum = (sum + buffer[l]) & 0xff;
  162. if (sum == buffer[63])
  163. valid = 1;
  164. else
  165. printf("Invalid checksum in EEPROM %02x %02x\n",
  166. sum, buffer[63]);
  167. }
  168. if (valid == 0) {
  169. memcpy(buffer, (void *)&default_spd_eeprom, len);
  170. sum = 0;
  171. for (l = 0; l < 63; l++)
  172. sum = (sum + buffer[l]) & 0xff;
  173. if (sum != buffer[63])
  174. printf("Invalid checksum in FLASH %02x %02x\n",
  175. sum, buffer[63]);
  176. buffer[63] = sum;
  177. }
  178. i2c_set_bus_num(old_bus);
  179. return 0;
  180. }