dh_imx6_spl.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DHCOM DH-iMX6 PDK SPL support
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/io.h>
  20. #include <errno.h>
  21. #include <fuse.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <i2c.h>
  24. #include <mmc.h>
  25. #include <spl.h>
  26. #define ENET_PAD_CTRL \
  27. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  28. PAD_CTL_HYS)
  29. #define GPIO_PAD_CTRL \
  30. (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  31. #define SPI_PAD_CTRL \
  32. (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33. PAD_CTL_SRE_FAST)
  34. #define UART_PAD_CTRL \
  35. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define USDHC_PAD_CTRL \
  38. (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
  41. .dram_sdclk_0 = 0x00020030,
  42. .dram_sdclk_1 = 0x00020030,
  43. .dram_cas = 0x00020030,
  44. .dram_ras = 0x00020030,
  45. .dram_reset = 0x00020030,
  46. .dram_sdcke0 = 0x00003000,
  47. .dram_sdcke1 = 0x00003000,
  48. .dram_sdba2 = 0x00000000,
  49. .dram_sdodt0 = 0x00003030,
  50. .dram_sdodt1 = 0x00003030,
  51. .dram_sdqs0 = 0x00000030,
  52. .dram_sdqs1 = 0x00000030,
  53. .dram_sdqs2 = 0x00000030,
  54. .dram_sdqs3 = 0x00000030,
  55. .dram_sdqs4 = 0x00000030,
  56. .dram_sdqs5 = 0x00000030,
  57. .dram_sdqs6 = 0x00000030,
  58. .dram_sdqs7 = 0x00000030,
  59. .dram_dqm0 = 0x00020030,
  60. .dram_dqm1 = 0x00020030,
  61. .dram_dqm2 = 0x00020030,
  62. .dram_dqm3 = 0x00020030,
  63. .dram_dqm4 = 0x00020030,
  64. .dram_dqm5 = 0x00020030,
  65. .dram_dqm6 = 0x00020030,
  66. .dram_dqm7 = 0x00020030,
  67. };
  68. static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
  69. .grp_ddr_type = 0x000C0000,
  70. .grp_ddrmode_ctl = 0x00020000,
  71. .grp_ddrpke = 0x00000000,
  72. .grp_addds = 0x00000030,
  73. .grp_ctlds = 0x00000030,
  74. .grp_ddrmode = 0x00020000,
  75. .grp_b0ds = 0x00000030,
  76. .grp_b1ds = 0x00000030,
  77. .grp_b2ds = 0x00000030,
  78. .grp_b3ds = 0x00000030,
  79. .grp_b4ds = 0x00000030,
  80. .grp_b5ds = 0x00000030,
  81. .grp_b6ds = 0x00000030,
  82. .grp_b7ds = 0x00000030,
  83. };
  84. static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
  85. .dram_sdclk_0 = 0x00020030,
  86. .dram_sdclk_1 = 0x00020030,
  87. .dram_cas = 0x00020030,
  88. .dram_ras = 0x00020030,
  89. .dram_reset = 0x00020030,
  90. .dram_sdcke0 = 0x00003000,
  91. .dram_sdcke1 = 0x00003000,
  92. .dram_sdba2 = 0x00000000,
  93. .dram_sdodt0 = 0x00003030,
  94. .dram_sdodt1 = 0x00003030,
  95. .dram_sdqs0 = 0x00000030,
  96. .dram_sdqs1 = 0x00000030,
  97. .dram_sdqs2 = 0x00000030,
  98. .dram_sdqs3 = 0x00000030,
  99. .dram_sdqs4 = 0x00000030,
  100. .dram_sdqs5 = 0x00000030,
  101. .dram_sdqs6 = 0x00000030,
  102. .dram_sdqs7 = 0x00000030,
  103. .dram_dqm0 = 0x00020030,
  104. .dram_dqm1 = 0x00020030,
  105. .dram_dqm2 = 0x00020030,
  106. .dram_dqm3 = 0x00020030,
  107. .dram_dqm4 = 0x00020030,
  108. .dram_dqm5 = 0x00020030,
  109. .dram_dqm6 = 0x00020030,
  110. .dram_dqm7 = 0x00020030,
  111. };
  112. static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
  113. .grp_ddr_type = 0x000C0000,
  114. .grp_ddrmode_ctl = 0x00020000,
  115. .grp_ddrpke = 0x00000000,
  116. .grp_addds = 0x00000030,
  117. .grp_ctlds = 0x00000030,
  118. .grp_ddrmode = 0x00020000,
  119. .grp_b0ds = 0x00000030,
  120. .grp_b1ds = 0x00000030,
  121. .grp_b2ds = 0x00000030,
  122. .grp_b3ds = 0x00000030,
  123. .grp_b4ds = 0x00000030,
  124. .grp_b5ds = 0x00000030,
  125. .grp_b6ds = 0x00000030,
  126. .grp_b7ds = 0x00000030,
  127. };
  128. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
  129. .p0_mpwldectrl0 = 0x00150019,
  130. .p0_mpwldectrl1 = 0x001C000B,
  131. .p1_mpwldectrl0 = 0x00020018,
  132. .p1_mpwldectrl1 = 0x0002000C,
  133. .p0_mpdgctrl0 = 0x43140320,
  134. .p0_mpdgctrl1 = 0x03080304,
  135. .p1_mpdgctrl0 = 0x43180320,
  136. .p1_mpdgctrl1 = 0x03100254,
  137. .p0_mprddlctl = 0x4830383C,
  138. .p1_mprddlctl = 0x3836323E,
  139. .p0_mpwrdlctl = 0x3E444642,
  140. .p1_mpwrdlctl = 0x42344442,
  141. };
  142. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
  143. .p0_mpwldectrl0 = 0x0040003C,
  144. .p0_mpwldectrl1 = 0x0032003E,
  145. .p0_mpdgctrl0 = 0x42350231,
  146. .p0_mpdgctrl1 = 0x021A0218,
  147. .p0_mprddlctl = 0x4B4B4E49,
  148. .p0_mpwrdlctl = 0x3F3F3035,
  149. };
  150. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
  151. .p0_mpwldectrl0 = 0x001a001a,
  152. .p0_mpwldectrl1 = 0x00260015,
  153. .p0_mpdgctrl0 = 0x030c0320,
  154. .p0_mpdgctrl1 = 0x03100304,
  155. .p0_mprddlctl = 0x432e3538,
  156. .p0_mpwrdlctl = 0x363f423d,
  157. .p1_mpwldectrl0 = 0x0006001e,
  158. .p1_mpwldectrl1 = 0x00050015,
  159. .p1_mpdgctrl0 = 0x031c0324,
  160. .p1_mpdgctrl1 = 0x030c0258,
  161. .p1_mprddlctl = 0x3834313f,
  162. .p1_mpwrdlctl = 0x47374a42,
  163. };
  164. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
  165. .p0_mpwldectrl0 = 0x003A003A,
  166. .p0_mpwldectrl1 = 0x0030002F,
  167. .p1_mpwldectrl0 = 0x002F0038,
  168. .p1_mpwldectrl1 = 0x00270039,
  169. .p0_mpdgctrl0 = 0x420F020F,
  170. .p0_mpdgctrl1 = 0x01760175,
  171. .p1_mpdgctrl0 = 0x41640171,
  172. .p1_mpdgctrl1 = 0x015E0160,
  173. .p0_mprddlctl = 0x45464B4A,
  174. .p1_mprddlctl = 0x49484A46,
  175. .p0_mpwrdlctl = 0x40402E32,
  176. .p1_mpwrdlctl = 0x3A3A3231,
  177. };
  178. static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
  179. .p0_mpwldectrl0 = 0x0040003C,
  180. .p0_mpwldectrl1 = 0x0032003E,
  181. .p0_mpdgctrl0 = 0x42350231,
  182. .p0_mpdgctrl1 = 0x021A0218,
  183. .p0_mprddlctl = 0x4B4B4E49,
  184. .p0_mpwrdlctl = 0x3F3F3035,
  185. };
  186. /*
  187. * 2 Gbit DDR3 memory
  188. * - NANYA #NT5CC128M16IP-DII
  189. * - NANYA #NT5CB128M16FP-DII
  190. */
  191. static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
  192. .mem_speed = 1600,
  193. .density = 2,
  194. .width = 16,
  195. .banks = 8,
  196. .rowaddr = 14,
  197. .coladdr = 10,
  198. .pagesz = 2,
  199. .trcd = 1375,
  200. .trcmin = 5863,
  201. .trasmin = 3750,
  202. };
  203. /*
  204. * 4 Gbit DDR3 memory
  205. * - Intelligent Memory #IM4G16D3EABG-125I
  206. */
  207. static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
  208. .mem_speed = 1600,
  209. .density = 4,
  210. .width = 16,
  211. .banks = 8,
  212. .rowaddr = 15,
  213. .coladdr = 10,
  214. .pagesz = 2,
  215. .trcd = 1375,
  216. .trcmin = 4875,
  217. .trasmin = 3500,
  218. };
  219. /* DDR3 64bit */
  220. static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
  221. /* width of data bus:0=16,1=32,2=64 */
  222. .dsize = 2,
  223. .cs_density = 32,
  224. .ncs = 1, /* single chip select */
  225. .cs1_mirror = 1,
  226. .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
  227. .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
  228. .walat = 1, /* Write additional latency */
  229. .ralat = 5, /* Read additional latency */
  230. .mif3_mode = 3, /* Command prediction working mode */
  231. .bi_on = 1, /* Bank interleaving enabled */
  232. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  233. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  234. .refsel = 1, /* Refresh cycles at 32KHz */
  235. .refr = 3, /* 4 refresh commands per refresh cycle */
  236. };
  237. /* DDR3 32bit */
  238. static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
  239. /* width of data bus:0=16,1=32,2=64 */
  240. .dsize = 1,
  241. .cs_density = 32,
  242. .ncs = 1, /* single chip select */
  243. .cs1_mirror = 1,
  244. .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
  245. .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
  246. .walat = 1, /* Write additional latency */
  247. .ralat = 5, /* Read additional latency */
  248. .mif3_mode = 3, /* Command prediction working mode */
  249. .bi_on = 1, /* Bank interleaving enabled */
  250. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  251. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  252. .refsel = 1, /* Refresh cycles at 32KHz */
  253. .refr = 3, /* 4 refresh commands per refresh cycle */
  254. };
  255. static void ccgr_init(void)
  256. {
  257. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  258. writel(0x00C03F3F, &ccm->CCGR0);
  259. writel(0x0030FC03, &ccm->CCGR1);
  260. writel(0x0FFFC000, &ccm->CCGR2);
  261. writel(0x3FF00000, &ccm->CCGR3);
  262. writel(0x00FFF300, &ccm->CCGR4);
  263. writel(0x0F0000C3, &ccm->CCGR5);
  264. writel(0x000003FF, &ccm->CCGR6);
  265. }
  266. /* Board ID */
  267. static iomux_v3_cfg_t const hwcode_pads[] = {
  268. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  269. IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  270. IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  271. };
  272. static void setup_iomux_boardid(void)
  273. {
  274. /* HW code pins: Setup alternate function and configure pads */
  275. SETUP_IOMUX_PADS(hwcode_pads);
  276. }
  277. /* DDR Code */
  278. static iomux_v3_cfg_t const ddrcode_pads[] = {
  279. IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  280. IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  281. };
  282. static void setup_iomux_ddrcode(void)
  283. {
  284. /* ddr code pins */
  285. SETUP_IOMUX_PADS(ddrcode_pads);
  286. }
  287. enum dhcom_ddr3_code {
  288. DH_DDR3_SIZE_256MIB = 0x00,
  289. DH_DDR3_SIZE_512MIB = 0x01,
  290. DH_DDR3_SIZE_1GIB = 0x02,
  291. DH_DDR3_SIZE_2GIB = 0x03
  292. };
  293. #define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
  294. #define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
  295. enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
  296. {
  297. enum dhcom_ddr3_code ddr3_code;
  298. gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
  299. gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
  300. gpio_direction_input(DDR3_CODE_BIT_0);
  301. gpio_direction_input(DDR3_CODE_BIT_1);
  302. /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
  303. ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
  304. | (!!gpio_get_value(DDR3_CODE_BIT_0));
  305. return ddr3_code;
  306. }
  307. /* GPIO */
  308. static iomux_v3_cfg_t const gpio_pads[] = {
  309. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  310. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  311. IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  312. IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  313. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  314. IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  315. IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  316. IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  317. IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  318. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  319. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  320. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  321. IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  322. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  323. IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  324. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  325. IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  326. IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  327. IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  328. IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  329. IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  330. IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  331. IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
  332. };
  333. static void setup_iomux_gpio(void)
  334. {
  335. SETUP_IOMUX_PADS(gpio_pads);
  336. }
  337. /* Ethernet */
  338. static iomux_v3_cfg_t const enet_pads[] = {
  339. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  340. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  341. IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  342. IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  343. IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  344. IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  345. IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  346. IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  347. IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  348. IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  349. /* SMSC PHY Reset */
  350. IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  351. /* ENET_VIO_GPIO */
  352. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  353. /* ENET_Interrupt - (not used) */
  354. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  355. };
  356. static void setup_iomux_enet(void)
  357. {
  358. SETUP_IOMUX_PADS(enet_pads);
  359. }
  360. /* SD interface */
  361. static iomux_v3_cfg_t const usdhc2_pads[] = {
  362. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  363. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  364. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  365. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  366. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  367. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  368. IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  369. };
  370. /* onboard microSD */
  371. static iomux_v3_cfg_t const usdhc3_pads[] = {
  372. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  373. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  374. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  375. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  376. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  377. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  378. IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  379. };
  380. /* eMMC */
  381. static iomux_v3_cfg_t const usdhc4_pads[] = {
  382. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  383. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  384. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  385. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  386. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  387. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  388. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  389. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  390. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  391. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  392. };
  393. /* SD */
  394. static void setup_iomux_sd(void)
  395. {
  396. SETUP_IOMUX_PADS(usdhc2_pads);
  397. SETUP_IOMUX_PADS(usdhc3_pads);
  398. SETUP_IOMUX_PADS(usdhc4_pads);
  399. }
  400. /* SPI */
  401. static iomux_v3_cfg_t const ecspi1_pads[] = {
  402. /* SS0 - SS of boot flash */
  403. IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
  404. MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
  405. /* SS2 - SS of DHCOM SPI1 */
  406. IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
  407. MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
  408. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  409. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  410. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  411. };
  412. static void setup_iomux_spi(void)
  413. {
  414. SETUP_IOMUX_PADS(ecspi1_pads);
  415. }
  416. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  417. {
  418. if (bus == 0 && cs == 0)
  419. return IMX_GPIO_NR(2, 30);
  420. else
  421. return -1;
  422. }
  423. /* UART */
  424. static iomux_v3_cfg_t const uart1_pads[] = {
  425. IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  426. IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  427. };
  428. static void setup_iomux_uart(void)
  429. {
  430. SETUP_IOMUX_PADS(uart1_pads);
  431. }
  432. #ifdef CONFIG_FSL_USDHC
  433. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  434. {USDHC4_BASE_ADDR},
  435. };
  436. int board_mmc_get_env_dev(int devno)
  437. {
  438. return devno - 1;
  439. }
  440. int board_mmc_getcd(struct mmc *mmc)
  441. {
  442. return 1; /* eMMC/uSDHC4 is always present */
  443. }
  444. int board_mmc_init(bd_t *bis)
  445. {
  446. SETUP_IOMUX_PADS(usdhc4_pads);
  447. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  448. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  449. usdhc_cfg[0].max_bus_width = 8;
  450. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  451. }
  452. #endif
  453. /* USB */
  454. static iomux_v3_cfg_t const usb_pads[] = {
  455. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  456. IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  457. };
  458. static void setup_iomux_usb(void)
  459. {
  460. SETUP_IOMUX_PADS(usb_pads);
  461. }
  462. /* Perform DDR DRAM calibration */
  463. static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  464. {
  465. int ret = 0;
  466. #ifdef CONFIG_MX6_DDRCAL
  467. udelay(100);
  468. ret = mmdc_do_write_level_calibration(sysinfo);
  469. if (ret) {
  470. printf("DDR3: Write level calibration error [%d]\n", ret);
  471. return ret;
  472. }
  473. ret = mmdc_do_dqs_calibration(sysinfo);
  474. if (ret) {
  475. printf("DDR3: DQS calibration error [%d]\n", ret);
  476. return ret;
  477. }
  478. #endif /* CONFIG_MX6_DDRCAL */
  479. return ret;
  480. }
  481. /* DRAM */
  482. static void dhcom_spl_dram_init(void)
  483. {
  484. enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
  485. if (is_mx6dq()) {
  486. mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
  487. &dhcom6dq_grp_ioregs);
  488. switch (ddr3_code) {
  489. default:
  490. printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
  491. printf(" choosing 1024 MB\n");
  492. /* fall through */
  493. case DH_DDR3_SIZE_1GIB:
  494. mx6_dram_cfg(&dhcom_ddr_64bit,
  495. &dhcom_mmdc_calib_4x2g_1066,
  496. &dhcom_mem_ddr_2g);
  497. break;
  498. case DH_DDR3_SIZE_2GIB:
  499. mx6_dram_cfg(&dhcom_ddr_64bit,
  500. &dhcom_mmdc_calib_4x4g_1066,
  501. &dhcom_mem_ddr_4g);
  502. break;
  503. }
  504. /* Perform DDR DRAM calibration */
  505. spl_dram_perform_cal(&dhcom_ddr_64bit);
  506. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  507. mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
  508. &dhcom6sdl_grp_ioregs);
  509. switch (ddr3_code) {
  510. default:
  511. printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
  512. printf(" choosing 1024 MB\n");
  513. /* fall through */
  514. case DH_DDR3_SIZE_1GIB:
  515. mx6_dram_cfg(&dhcom_ddr_64bit,
  516. &dhcom_mmdc_calib_4x2g_800,
  517. &dhcom_mem_ddr_2g);
  518. break;
  519. }
  520. /* Perform DDR DRAM calibration */
  521. spl_dram_perform_cal(&dhcom_ddr_64bit);
  522. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  523. mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
  524. &dhcom6sdl_grp_ioregs);
  525. switch (ddr3_code) {
  526. default:
  527. printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
  528. printf(" choosing 512 MB\n");
  529. /* fall through */
  530. case DH_DDR3_SIZE_512MIB:
  531. mx6_dram_cfg(&dhcom_ddr_32bit,
  532. &dhcom_mmdc_calib_2x2g_800,
  533. &dhcom_mem_ddr_2g);
  534. break;
  535. case DH_DDR3_SIZE_1GIB:
  536. mx6_dram_cfg(&dhcom_ddr_32bit,
  537. &dhcom_mmdc_calib_2x4g_800,
  538. &dhcom_mem_ddr_4g);
  539. break;
  540. }
  541. /* Perform DDR DRAM calibration */
  542. spl_dram_perform_cal(&dhcom_ddr_32bit);
  543. }
  544. }
  545. void board_init_f(ulong dummy)
  546. {
  547. /* setup AIPS and disable watchdog */
  548. arch_cpu_init();
  549. ccgr_init();
  550. gpr_init();
  551. /* setup GP timer */
  552. timer_init();
  553. setup_iomux_boardid();
  554. setup_iomux_ddrcode();
  555. setup_iomux_gpio();
  556. setup_iomux_enet();
  557. setup_iomux_sd();
  558. setup_iomux_spi();
  559. setup_iomux_uart();
  560. setup_iomux_usb();
  561. /* UART clocks enabled and gd valid - init serial console */
  562. preloader_console_init();
  563. /* DDR3 initialization */
  564. dhcom_spl_dram_init();
  565. /* Clear the BSS. */
  566. memset(__bss_start, 0, __bss_end - __bss_start);
  567. /* load/boot image from boot device */
  568. board_init_r(NULL, 0);
  569. }