dh_imx6.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DHCOM DH-iMX6 PDK board support
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <eeprom.h>
  10. #include <init.h>
  11. #include <dm/device-internal.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/sata.h>
  23. #include <ahci.h>
  24. #include <dwc_ahsata.h>
  25. #include <env.h>
  26. #include <errno.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <fuse.h>
  29. #include <i2c_eeprom.h>
  30. #include <miiphy.h>
  31. #include <mmc.h>
  32. #include <net.h>
  33. #include <netdev.h>
  34. #include <usb.h>
  35. #include <usb/ehci-ci.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. int dram_init(void)
  38. {
  39. gd->ram_size = imx_ddr_size();
  40. return 0;
  41. }
  42. /*
  43. * Do not overwrite the console
  44. * Use always serial for U-Boot console
  45. */
  46. int overwrite_console(void)
  47. {
  48. return 1;
  49. }
  50. #ifdef CONFIG_FEC_MXC
  51. static void eth_phy_reset(void)
  52. {
  53. /* Reset PHY */
  54. gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
  55. udelay(500);
  56. gpio_set_value(IMX_GPIO_NR(5, 0), 1);
  57. /* Enable VIO */
  58. gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
  59. /*
  60. * KSZ9021 PHY needs at least 10 mSec after PHY reset
  61. * is released to stabilize
  62. */
  63. mdelay(10);
  64. }
  65. static int setup_fec_clock(void)
  66. {
  67. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  68. /* set gpr1[21] to select anatop clock */
  69. clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
  70. return enable_fec_anatop_clock(0, ENET_50MHZ);
  71. }
  72. int board_eth_init(bd_t *bis)
  73. {
  74. uint32_t base = IMX_FEC_BASE;
  75. struct mii_dev *bus = NULL;
  76. struct phy_device *phydev = NULL;
  77. gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
  78. gpio_request(IMX_GPIO_NR(1, 7), "VIO");
  79. setup_fec_clock();
  80. eth_phy_reset();
  81. bus = fec_get_miibus(base, -1);
  82. if (!bus)
  83. return -EINVAL;
  84. /* Scan PHY 0 */
  85. phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
  86. if (!phydev) {
  87. printf("Ethernet PHY not found!\n");
  88. return -EINVAL;
  89. }
  90. return fec_probe(bis, -1, base, bus, phydev);
  91. }
  92. #endif
  93. #ifdef CONFIG_USB_EHCI_MX6
  94. static void setup_usb(void)
  95. {
  96. /*
  97. * Set daisy chain for otg_pin_id on MX6Q.
  98. * For MX6DL, this bit is reserved.
  99. */
  100. imx_iomux_set_gpr_register(1, 13, 1, 0);
  101. }
  102. int board_usb_phy_mode(int port)
  103. {
  104. if (port == 1)
  105. return USB_INIT_HOST;
  106. else
  107. return USB_INIT_DEVICE;
  108. }
  109. #endif
  110. static int setup_dhcom_mac_from_fuse(void)
  111. {
  112. struct udevice *dev;
  113. ofnode eeprom;
  114. unsigned char enetaddr[6];
  115. int ret;
  116. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  117. if (ret) /* ethaddr is already set */
  118. return 0;
  119. imx_get_mac_from_fuse(0, enetaddr);
  120. if (is_valid_ethaddr(enetaddr)) {
  121. eth_env_set_enetaddr("ethaddr", enetaddr);
  122. return 0;
  123. }
  124. eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
  125. if (!ofnode_valid(eeprom)) {
  126. printf("Invalid hardware path to EEPROM!\n");
  127. return -ENODEV;
  128. }
  129. ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
  130. if (ret) {
  131. printf("Cannot find EEPROM!\n");
  132. return ret;
  133. }
  134. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  135. if (ret) {
  136. printf("Error reading configuration EEPROM!\n");
  137. return ret;
  138. }
  139. if (is_valid_ethaddr(enetaddr))
  140. eth_env_set_enetaddr("ethaddr", enetaddr);
  141. return 0;
  142. }
  143. int board_early_init_f(void)
  144. {
  145. #ifdef CONFIG_USB_EHCI_MX6
  146. setup_usb();
  147. #endif
  148. return 0;
  149. }
  150. int board_init(void)
  151. {
  152. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  153. /* address of boot parameters */
  154. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  155. /* Enable eim_slow clocks */
  156. setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  157. setup_dhcom_mac_from_fuse();
  158. return 0;
  159. }
  160. #ifdef CONFIG_CMD_BMODE
  161. static const struct boot_mode board_boot_modes[] = {
  162. /* 4 bit bus width */
  163. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  164. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  165. /* 8 bit bus width */
  166. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  167. {NULL, 0},
  168. };
  169. #endif
  170. #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
  171. #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
  172. #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
  173. static int board_get_hwcode(void)
  174. {
  175. int hw_code;
  176. gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
  177. gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
  178. gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
  179. gpio_direction_input(HW_CODE_BIT_0);
  180. gpio_direction_input(HW_CODE_BIT_1);
  181. gpio_direction_input(HW_CODE_BIT_2);
  182. /* HW 100 + HW 200 = 00b; HW 300 = 01b */
  183. hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
  184. (gpio_get_value(HW_CODE_BIT_1) << 1) |
  185. gpio_get_value(HW_CODE_BIT_0)) + 2;
  186. return hw_code;
  187. }
  188. int board_late_init(void)
  189. {
  190. u32 hw_code;
  191. char buf[16];
  192. hw_code = board_get_hwcode();
  193. switch (get_cpu_type()) {
  194. case MXC_CPU_MX6SOLO:
  195. snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
  196. break;
  197. case MXC_CPU_MX6DL:
  198. snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
  199. break;
  200. case MXC_CPU_MX6D:
  201. snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
  202. break;
  203. case MXC_CPU_MX6Q:
  204. snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
  205. break;
  206. default:
  207. snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
  208. break;
  209. }
  210. env_set("dhcom", buf);
  211. #ifdef CONFIG_CMD_BMODE
  212. add_board_boot_modes(board_boot_modes);
  213. #endif
  214. return 0;
  215. }
  216. int checkboard(void)
  217. {
  218. puts("Board: DHCOM i.MX6\n");
  219. return 0;
  220. }
  221. #ifdef CONFIG_MULTI_DTB_FIT
  222. int board_fit_config_name_match(const char *name)
  223. {
  224. if (is_mx6dq()) {
  225. if (!strcmp(name, "imx6q-dhcom-pdk2"))
  226. return 0;
  227. } else if (is_mx6sdl()) {
  228. if (!strcmp(name, "imx6dl-dhcom-pdk2"))
  229. return 0;
  230. }
  231. return -1;
  232. }
  233. #endif