nand.c 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2017 CS Systemes d'Information
  4. * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
  5. * Christophe Leroy <christophe.leroy@c-s.fr>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <nand.h>
  10. #include <asm/io.h>
  11. #define BIT_CLE ((unsigned short)0x0800)
  12. #define BIT_ALE ((unsigned short)0x0400)
  13. #define BIT_NCE ((unsigned short)0x1000)
  14. static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
  15. {
  16. struct nand_chip *this = mtd_to_nand(mtdinfo);
  17. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  18. unsigned short pddat = 0;
  19. /* The hardware control change */
  20. if (ctrl & NAND_CTRL_CHANGE) {
  21. pddat = in_be16(&immr->im_ioport.iop_pddat);
  22. /* Clearing ALE and CLE */
  23. pddat &= ~(BIT_CLE | BIT_ALE);
  24. /* Driving NCE pin */
  25. if (ctrl & NAND_NCE)
  26. pddat &= ~BIT_NCE;
  27. else
  28. pddat |= BIT_NCE;
  29. /* Driving CLE and ALE pin */
  30. if (ctrl & NAND_CLE)
  31. pddat |= BIT_CLE;
  32. if (ctrl & NAND_ALE)
  33. pddat |= BIT_ALE;
  34. out_be16(&immr->im_ioport.iop_pddat, pddat);
  35. }
  36. /* Writing the command */
  37. if (cmd != NAND_CMD_NONE)
  38. out_8(this->IO_ADDR_W, cmd);
  39. }
  40. int board_nand_init(struct nand_chip *nand)
  41. {
  42. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  43. /* Set GPIO Port */
  44. setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
  45. clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
  46. clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
  47. nand->chip_delay = 60;
  48. nand->ecc.mode = NAND_ECC_SOFT;
  49. nand->cmd_ctrl = nand_hwcontrol;
  50. return 0;
  51. }