xfi3.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Creative ZEN X-Fi3 board
  4. *
  5. * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  6. *
  7. * Hardware investigation done by:
  8. *
  9. * Amaury Pouly <amaury.pouly@gmail.com>
  10. */
  11. #include <common.h>
  12. #include <errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/iomux-mx23.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /*
  21. * Functions
  22. */
  23. int board_early_init_f(void)
  24. {
  25. /* IO0 clock at 480MHz */
  26. mxs_set_ioclk(MXC_IOCLK0, 480000);
  27. /* SSP0 clock at 96MHz */
  28. mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
  29. return 0;
  30. }
  31. int dram_init(void)
  32. {
  33. return mxs_dram_init();
  34. }
  35. #ifdef CONFIG_CMD_MMC
  36. static int xfi3_mmc_cd(int id)
  37. {
  38. switch (id) {
  39. case 0:
  40. /* The SSP_DETECT is inverted on this board. */
  41. return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
  42. case 1:
  43. /* Phison bridge always present */
  44. return 1;
  45. default:
  46. return 0;
  47. }
  48. }
  49. int board_mmc_init(bd_t *bis)
  50. {
  51. int ret;
  52. /* MicroSD slot */
  53. gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
  54. gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
  55. ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
  56. if (ret)
  57. return ret;
  58. /* Phison SD-NAND bridge */
  59. ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
  60. return ret;
  61. }
  62. #endif
  63. #ifdef CONFIG_VIDEO_MXS
  64. static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
  65. {
  66. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  67. const unsigned int timeout = 0x10000;
  68. if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
  69. timeout))
  70. return -ETIMEDOUT;
  71. writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
  72. (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
  73. &regs->hw_lcdif_transfer_count);
  74. writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
  75. &regs->hw_lcdif_ctrl_clr);
  76. if (data)
  77. writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
  78. writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  79. if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
  80. timeout))
  81. return -ETIMEDOUT;
  82. writel(payload, &regs->hw_lcdif_data);
  83. return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
  84. timeout);
  85. }
  86. static void mxsfb_write_register(uint32_t reg, uint32_t data)
  87. {
  88. mxsfb_write_byte(reg, 0);
  89. mxsfb_write_byte(data, 1);
  90. }
  91. static const struct {
  92. uint8_t reg;
  93. uint8_t delay;
  94. uint16_t val;
  95. } lcd_regs[] = {
  96. { 0x01, 0, 0x001c },
  97. { 0x02, 0, 0x0100 },
  98. /* Writing 0x30 to reg. 0x03 flips the LCD */
  99. { 0x03, 0, 0x1038 },
  100. { 0x08, 0, 0x0808 },
  101. /* This can contain 0x111 to rotate the LCD. */
  102. { 0x0c, 0, 0x0000 },
  103. { 0x0f, 0, 0x0c01 },
  104. { 0x20, 0, 0x0000 },
  105. { 0x21, 30, 0x0000 },
  106. /* Wait 30 mS here */
  107. { 0x10, 0, 0x0a00 },
  108. { 0x11, 30, 0x1038 },
  109. /* Wait 30 mS here */
  110. { 0x12, 0, 0x1010 },
  111. { 0x13, 0, 0x0050 },
  112. { 0x14, 0, 0x4f58 },
  113. { 0x30, 0, 0x0000 },
  114. { 0x31, 0, 0x00db },
  115. { 0x32, 0, 0x0000 },
  116. { 0x33, 0, 0x0000 },
  117. { 0x34, 0, 0x00db },
  118. { 0x35, 0, 0x0000 },
  119. { 0x36, 0, 0x00af },
  120. { 0x37, 0, 0x0000 },
  121. { 0x38, 0, 0x00db },
  122. { 0x39, 0, 0x0000 },
  123. { 0x50, 0, 0x0000 },
  124. { 0x51, 0, 0x0705 },
  125. { 0x52, 0, 0x0e0a },
  126. { 0x53, 0, 0x0300 },
  127. { 0x54, 0, 0x0a0e },
  128. { 0x55, 0, 0x0507 },
  129. { 0x56, 0, 0x0000 },
  130. { 0x57, 0, 0x0003 },
  131. { 0x58, 0, 0x090a },
  132. { 0x59, 30, 0x0a09 },
  133. /* Wait 30 mS here */
  134. { 0x07, 30, 0x1017 },
  135. /* Wait 40 mS here */
  136. { 0x36, 0, 0x00af },
  137. { 0x37, 0, 0x0000 },
  138. { 0x38, 0, 0x00db },
  139. { 0x39, 0, 0x0000 },
  140. { 0x20, 0, 0x0000 },
  141. { 0x21, 0, 0x0000 },
  142. };
  143. void mxsfb_system_setup(void)
  144. {
  145. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  146. int i;
  147. /* Switch the LCDIF into System-Mode */
  148. writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
  149. LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
  150. /* Restart the SmartLCD controller */
  151. mdelay(50);
  152. writel(1, &regs->hw_lcdif_ctrl1_set);
  153. mdelay(50);
  154. writel(1, &regs->hw_lcdif_ctrl1_clr);
  155. mdelay(50);
  156. writel(1, &regs->hw_lcdif_ctrl1_set);
  157. mdelay(50);
  158. /* Program the SmartLCD controller */
  159. writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
  160. writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
  161. (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
  162. (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
  163. (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
  164. &regs->hw_lcdif_timing);
  165. /*
  166. * OTM2201A init and configuration sequence.
  167. */
  168. for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
  169. mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
  170. if (lcd_regs[i].delay)
  171. mdelay(lcd_regs[i].delay);
  172. }
  173. /* Turn on Framebuffer Upload Mode */
  174. mxsfb_write_byte(0x22, 0);
  175. writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
  176. &regs->hw_lcdif_ctrl_set);
  177. }
  178. #endif
  179. int board_init(void)
  180. {
  181. /* Adress of boot parameters */
  182. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  183. /* Turn on PWM backlight */
  184. gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
  185. return 0;
  186. }
  187. int board_eth_init(bd_t *bis)
  188. {
  189. usb_eth_initialize(bis);
  190. return 0;
  191. }