spl.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SPL specific code for Compulab CM-T335 board
  4. *
  5. * Board functions for Compulab CM-T335 board
  6. *
  7. * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
  8. *
  9. * Author: Ilya Ledvich <ilya@compulab.co.il>
  10. */
  11. #include <common.h>
  12. #include <errno.h>
  13. #include <asm/arch/ddr_defs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/clocks_am33xx.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/hardware_am33xx.h>
  18. #include <linux/sizes.h>
  19. const struct ctrl_ioregs ioregs = {
  20. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  21. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  22. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  23. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  24. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  25. };
  26. static const struct ddr_data ddr3_data = {
  27. .datardsratio0 = MT41J128MJT125_RD_DQS,
  28. .datawdsratio0 = MT41J128MJT125_WR_DQS,
  29. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  30. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  31. };
  32. static const struct cmd_control ddr3_cmd_ctrl_data = {
  33. .cmd0csratio = MT41J128MJT125_RATIO,
  34. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  35. .cmd1csratio = MT41J128MJT125_RATIO,
  36. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  37. .cmd2csratio = MT41J128MJT125_RATIO,
  38. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  39. };
  40. static struct emif_regs ddr3_emif_reg_data = {
  41. .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  42. .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  43. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  44. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  45. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  46. .zq_config = MT41J128MJT125_ZQ_CFG,
  47. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  48. PHY_EN_DYN_PWRDN,
  49. };
  50. const struct dpll_params dpll_ddr = {
  51. /* M N M2 M3 M4 M5 M6 */
  52. 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
  53. void am33xx_spl_board_init(void)
  54. {
  55. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  56. /* Get the frequency */
  57. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  58. /* Set CORE Frequencies to OPP100 */
  59. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  60. /* Set MPU Frequency to what we detected now that voltages are set */
  61. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  62. }
  63. const struct dpll_params *get_dpll_ddr_params(void)
  64. {
  65. return &dpll_ddr;
  66. }
  67. static void probe_sdram_size(long size)
  68. {
  69. switch (size) {
  70. case SZ_512M:
  71. ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
  72. break;
  73. case SZ_256M:
  74. ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
  75. break;
  76. case SZ_128M:
  77. ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
  78. break;
  79. default:
  80. puts("Failed configuring DRAM, resetting...\n\n");
  81. reset_cpu(0);
  82. }
  83. debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
  84. config_ddr(303, &ioregs, &ddr3_data,
  85. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  86. }
  87. void sdram_init(void)
  88. {
  89. long size = SZ_1G;
  90. do {
  91. size = size / 2;
  92. probe_sdram_size(size);
  93. } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
  94. return;
  95. }