mux.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Pinmux configuration for Compulab CM-T335 board
  4. *
  5. * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Ilya Ledvich <ilya@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/mux.h>
  13. #include <asm/io.h>
  14. static struct module_pin_mux uart0_pin_mux[] = {
  15. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
  16. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  17. {-1},
  18. };
  19. static struct module_pin_mux uart1_pin_mux[] = {
  20. {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
  21. {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
  22. {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
  23. {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
  24. {-1},
  25. };
  26. static struct module_pin_mux mmc0_pin_mux[] = {
  27. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
  28. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
  29. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
  30. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  31. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
  32. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
  33. {-1},
  34. };
  35. static struct module_pin_mux i2c0_pin_mux[] = {
  36. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
  37. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
  38. {-1},
  39. };
  40. static struct module_pin_mux i2c1_pin_mux[] = {
  41. /* I2C_DATA */
  42. {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
  43. /* I2C_SCLK */
  44. {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
  45. {-1},
  46. };
  47. static struct module_pin_mux rgmii1_pin_mux[] = {
  48. {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  49. {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  50. {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  51. {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  52. {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  53. {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  54. {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  55. {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  56. {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  57. {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  58. {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  59. {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  60. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  61. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  62. {-1},
  63. };
  64. static struct module_pin_mux nand_pin_mux[] = {
  65. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  66. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  67. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  68. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  69. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  70. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  71. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  72. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  73. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  74. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  75. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  76. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  77. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  78. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  79. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  80. {-1},
  81. };
  82. static struct module_pin_mux eth_phy_rst_pin_mux[] = {
  83. {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
  84. {-1},
  85. };
  86. static struct module_pin_mux status_led_pin_mux[] = {
  87. {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
  88. {-1},
  89. };
  90. void set_uart_mux_conf(void)
  91. {
  92. configure_module_pin_mux(uart0_pin_mux);
  93. configure_module_pin_mux(uart1_pin_mux);
  94. }
  95. void set_mux_conf_regs(void)
  96. {
  97. configure_module_pin_mux(i2c0_pin_mux);
  98. configure_module_pin_mux(i2c1_pin_mux);
  99. configure_module_pin_mux(rgmii1_pin_mux);
  100. configure_module_pin_mux(eth_phy_rst_pin_mux);
  101. configure_module_pin_mux(mmc0_pin_mux);
  102. configure_module_pin_mux(nand_pin_mux);
  103. configure_module_pin_mux(status_led_pin_mux);
  104. }