nitrogen6x.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <malloc.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/sata.h>
  20. #include <asm/mach-imx/spi.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <asm/mach-imx/video.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <micrel.h>
  26. #include <miiphy.h>
  27. #include <netdev.h>
  28. #include <asm/arch/crm_regs.h>
  29. #include <asm/arch/mxc_hdmi.h>
  30. #include <i2c.h>
  31. #include <input.h>
  32. #include <netdev.h>
  33. #include <usb/ehci-ci.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  36. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  37. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  38. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  40. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  45. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  46. #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  50. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  51. #define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
  52. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  53. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  54. PAD_CTL_SRE_SLOW)
  55. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  56. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  57. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  58. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  59. /* Prevent compiler error if gpio number 08 or 09 is used */
  60. #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  61. #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  62. sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \
  63. .scl = { \
  64. .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  65. pad_ctrl), \
  66. .gpio_mode = NEW_PAD_CTRL( \
  67. cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  68. pad_ctrl), \
  69. .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \
  70. }, \
  71. .sda = { \
  72. .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  73. pad_ctrl), \
  74. .gpio_mode = NEW_PAD_CTRL( \
  75. cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  76. pad_ctrl), \
  77. .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \
  78. } \
  79. }
  80. #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  81. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  82. _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  83. sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
  84. #if defined(CONFIG_MX6QDL)
  85. #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
  86. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  87. I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \
  88. sda_pad, sda_bank, sda_gp, pad_ctrl), \
  89. I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \
  90. sda_pad, sda_bank, sda_gp, pad_ctrl)
  91. #define I2C_PADS_INFO_ENTRY_SPACING 2
  92. #define IOMUX_PAD_CTRL(name, pad_ctrl) \
  93. NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \
  94. NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
  95. #else
  96. #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
  97. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  98. I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \
  99. sda_pad, sda_bank, sda_gp, pad_ctrl)
  100. #define I2C_PADS_INFO_ENTRY_SPACING 1
  101. #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
  102. #endif
  103. int dram_init(void)
  104. {
  105. gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  106. return 0;
  107. }
  108. static iomux_v3_cfg_t const uart1_pads[] = {
  109. IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
  110. IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
  111. };
  112. static iomux_v3_cfg_t const uart2_pads[] = {
  113. IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
  114. IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
  115. };
  116. static struct i2c_pads_info i2c_pads[] = {
  117. /* I2C1, SGTL5000 */
  118. I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
  119. /* I2C2 Camera, MIPI */
  120. I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
  121. I2C_PAD_CTRL),
  122. /* I2C3, J15 - RGB connector */
  123. I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
  124. };
  125. #define I2C_BUS_CNT 3
  126. static iomux_v3_cfg_t const usdhc2_pads[] = {
  127. IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
  128. IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
  129. IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
  130. IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
  131. IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
  132. IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
  133. };
  134. static iomux_v3_cfg_t const usdhc3_pads[] = {
  135. IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
  136. IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
  137. IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
  138. IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
  139. IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
  140. IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
  141. IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
  142. };
  143. static iomux_v3_cfg_t const usdhc4_pads[] = {
  144. IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
  145. IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
  146. IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
  147. IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
  148. IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
  149. IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
  150. IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
  151. };
  152. static iomux_v3_cfg_t const enet_pads1[] = {
  153. IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
  154. IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
  155. IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
  156. IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
  157. IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
  158. IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
  159. IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
  160. IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
  161. IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
  162. /* pin 35 - 1 (PHY_AD2) on reset */
  163. IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
  164. /* pin 32 - 1 - (MODE0) all */
  165. IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
  166. /* pin 31 - 1 - (MODE1) all */
  167. IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
  168. /* pin 28 - 1 - (MODE2) all */
  169. IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
  170. /* pin 27 - 1 - (MODE3) all */
  171. IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
  172. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  173. IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
  174. /* pin 42 PHY nRST */
  175. IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
  176. IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
  177. };
  178. static iomux_v3_cfg_t const enet_pads2[] = {
  179. IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
  180. IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
  181. IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
  182. IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
  183. IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
  184. IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
  185. };
  186. static iomux_v3_cfg_t const misc_pads[] = {
  187. IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
  188. IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
  189. IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
  190. /* OTG Power enable */
  191. IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  192. };
  193. /* wl1271 pads on nitrogen6x */
  194. static iomux_v3_cfg_t const wl12xx_pads[] = {
  195. IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  196. IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  197. IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  198. };
  199. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  200. #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
  201. #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
  202. /* Button assignments for J14 */
  203. static iomux_v3_cfg_t const button_pads[] = {
  204. /* Menu */
  205. IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
  206. /* Back */
  207. IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
  208. /* Labelled Search (mapped to Power under Android) */
  209. IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
  210. /* Home */
  211. IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
  212. /* Volume Down */
  213. IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
  214. /* Volume Up */
  215. IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
  216. };
  217. static void setup_iomux_enet(void)
  218. {
  219. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
  220. gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
  221. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  222. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  223. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  224. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  225. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  226. SETUP_IOMUX_PADS(enet_pads1);
  227. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  228. /* Need delay 10ms according to KSZ9021 spec */
  229. udelay(1000 * 10);
  230. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
  231. gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
  232. SETUP_IOMUX_PADS(enet_pads2);
  233. udelay(100); /* Wait 100 us before using mii interface */
  234. }
  235. static iomux_v3_cfg_t const usb_pads[] = {
  236. IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
  237. };
  238. static void setup_iomux_uart(void)
  239. {
  240. SETUP_IOMUX_PADS(uart1_pads);
  241. SETUP_IOMUX_PADS(uart2_pads);
  242. }
  243. #ifdef CONFIG_USB_EHCI_MX6
  244. int board_ehci_hcd_init(int port)
  245. {
  246. SETUP_IOMUX_PADS(usb_pads);
  247. /* Reset USB hub */
  248. gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
  249. mdelay(2);
  250. gpio_set_value(IMX_GPIO_NR(7, 12), 1);
  251. return 0;
  252. }
  253. int board_ehci_power(int port, int on)
  254. {
  255. if (port)
  256. return 0;
  257. gpio_set_value(GP_USB_OTG_PWR, on);
  258. return 0;
  259. }
  260. #endif
  261. #ifdef CONFIG_FSL_ESDHC_IMX
  262. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  263. {USDHC3_BASE_ADDR},
  264. {USDHC4_BASE_ADDR},
  265. };
  266. int board_mmc_getcd(struct mmc *mmc)
  267. {
  268. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  269. int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
  270. IMX_GPIO_NR(2, 6);
  271. gpio_direction_input(gp_cd);
  272. return !gpio_get_value(gp_cd);
  273. }
  274. int board_mmc_init(bd_t *bis)
  275. {
  276. int ret;
  277. u32 index = 0;
  278. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  279. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  280. usdhc_cfg[0].max_bus_width = 4;
  281. usdhc_cfg[1].max_bus_width = 4;
  282. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  283. switch (index) {
  284. case 0:
  285. SETUP_IOMUX_PADS(usdhc3_pads);
  286. break;
  287. case 1:
  288. SETUP_IOMUX_PADS(usdhc4_pads);
  289. break;
  290. default:
  291. printf("Warning: you configured more USDHC controllers"
  292. "(%d) then supported by the board (%d)\n",
  293. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  294. return -EINVAL;
  295. }
  296. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  297. if (ret)
  298. return ret;
  299. }
  300. return 0;
  301. }
  302. #endif
  303. #ifdef CONFIG_MXC_SPI
  304. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  305. {
  306. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  307. }
  308. static iomux_v3_cfg_t const ecspi1_pads[] = {
  309. /* SS1 */
  310. IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
  311. IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
  312. IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
  313. IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
  314. };
  315. static void setup_spi(void)
  316. {
  317. SETUP_IOMUX_PADS(ecspi1_pads);
  318. }
  319. #endif
  320. int board_phy_config(struct phy_device *phydev)
  321. {
  322. /* min rx data delay */
  323. ksz9021_phy_extended_write(phydev,
  324. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  325. /* min tx data delay */
  326. ksz9021_phy_extended_write(phydev,
  327. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  328. /* max rx/tx clock delay, min rx/tx control */
  329. ksz9021_phy_extended_write(phydev,
  330. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  331. if (phydev->drv->config)
  332. phydev->drv->config(phydev);
  333. return 0;
  334. }
  335. int board_eth_init(bd_t *bis)
  336. {
  337. uint32_t base = IMX_FEC_BASE;
  338. struct mii_dev *bus = NULL;
  339. struct phy_device *phydev = NULL;
  340. int ret;
  341. gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
  342. gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
  343. gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
  344. gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
  345. gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
  346. gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
  347. gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
  348. gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
  349. gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
  350. setup_iomux_enet();
  351. #ifdef CONFIG_FEC_MXC
  352. bus = fec_get_miibus(base, -1);
  353. if (!bus)
  354. return -EINVAL;
  355. /* scan phy 4,5,6,7 */
  356. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  357. if (!phydev) {
  358. ret = -EINVAL;
  359. goto free_bus;
  360. }
  361. printf("using phy at %d\n", phydev->addr);
  362. ret = fec_probe(bis, -1, base, bus, phydev);
  363. if (ret)
  364. goto free_phydev;
  365. #endif
  366. #ifdef CONFIG_CI_UDC
  367. /* For otg ethernet*/
  368. usb_eth_initialize(bis);
  369. #endif
  370. return 0;
  371. free_phydev:
  372. free(phydev);
  373. free_bus:
  374. free(bus);
  375. return ret;
  376. }
  377. static void setup_buttons(void)
  378. {
  379. SETUP_IOMUX_PADS(button_pads);
  380. }
  381. #if defined(CONFIG_VIDEO_IPUV3)
  382. static iomux_v3_cfg_t const backlight_pads[] = {
  383. /* Backlight on RGB connector: J15 */
  384. IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
  385. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
  386. /* Backlight on LVDS connector: J6 */
  387. IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
  388. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
  389. };
  390. static iomux_v3_cfg_t const rgb_pads[] = {
  391. IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
  392. IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
  393. IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
  394. IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
  395. IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
  396. IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
  397. IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
  398. IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
  399. IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
  400. IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
  401. IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
  402. IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
  403. IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
  404. IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
  405. IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
  406. IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
  407. IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
  408. IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
  409. IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
  410. IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
  411. IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
  412. IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
  413. IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
  414. IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
  415. IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
  416. IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
  417. IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
  418. IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
  419. IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
  420. };
  421. static void do_enable_hdmi(struct display_info_t const *dev)
  422. {
  423. imx_enable_hdmi_phy();
  424. }
  425. static int detect_i2c(struct display_info_t const *dev)
  426. {
  427. return ((0 == i2c_set_bus_num(dev->bus))
  428. &&
  429. (0 == i2c_probe(dev->addr)));
  430. }
  431. static void enable_lvds(struct display_info_t const *dev)
  432. {
  433. struct iomuxc *iomux = (struct iomuxc *)
  434. IOMUXC_BASE_ADDR;
  435. u32 reg = readl(&iomux->gpr[2]);
  436. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  437. writel(reg, &iomux->gpr[2]);
  438. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  439. }
  440. static void enable_lvds_jeida(struct display_info_t const *dev)
  441. {
  442. struct iomuxc *iomux = (struct iomuxc *)
  443. IOMUXC_BASE_ADDR;
  444. u32 reg = readl(&iomux->gpr[2]);
  445. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  446. |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
  447. writel(reg, &iomux->gpr[2]);
  448. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  449. }
  450. static void enable_rgb(struct display_info_t const *dev)
  451. {
  452. SETUP_IOMUX_PADS(rgb_pads);
  453. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  454. }
  455. struct display_info_t const displays[] = {{
  456. .bus = 1,
  457. .addr = 0x50,
  458. .pixfmt = IPU_PIX_FMT_RGB24,
  459. .detect = detect_i2c,
  460. .enable = do_enable_hdmi,
  461. .mode = {
  462. .name = "HDMI",
  463. .refresh = 60,
  464. .xres = 1024,
  465. .yres = 768,
  466. .pixclock = 15385,
  467. .left_margin = 220,
  468. .right_margin = 40,
  469. .upper_margin = 21,
  470. .lower_margin = 7,
  471. .hsync_len = 60,
  472. .vsync_len = 10,
  473. .sync = FB_SYNC_EXT,
  474. .vmode = FB_VMODE_NONINTERLACED
  475. } }, {
  476. .bus = 0,
  477. .addr = 0,
  478. .pixfmt = IPU_PIX_FMT_RGB24,
  479. .detect = NULL,
  480. .enable = enable_lvds_jeida,
  481. .mode = {
  482. .name = "LDB-WXGA",
  483. .refresh = 60,
  484. .xres = 1280,
  485. .yres = 800,
  486. .pixclock = 14065,
  487. .left_margin = 40,
  488. .right_margin = 40,
  489. .upper_margin = 3,
  490. .lower_margin = 80,
  491. .hsync_len = 10,
  492. .vsync_len = 10,
  493. .sync = FB_SYNC_EXT,
  494. .vmode = FB_VMODE_NONINTERLACED
  495. } }, {
  496. .bus = 0,
  497. .addr = 0,
  498. .pixfmt = IPU_PIX_FMT_RGB24,
  499. .detect = NULL,
  500. .enable = enable_lvds,
  501. .mode = {
  502. .name = "LDB-WXGA-S",
  503. .refresh = 60,
  504. .xres = 1280,
  505. .yres = 800,
  506. .pixclock = 14065,
  507. .left_margin = 40,
  508. .right_margin = 40,
  509. .upper_margin = 3,
  510. .lower_margin = 80,
  511. .hsync_len = 10,
  512. .vsync_len = 10,
  513. .sync = FB_SYNC_EXT,
  514. .vmode = FB_VMODE_NONINTERLACED
  515. } }, {
  516. .bus = 2,
  517. .addr = 0x4,
  518. .pixfmt = IPU_PIX_FMT_LVDS666,
  519. .detect = detect_i2c,
  520. .enable = enable_lvds,
  521. .mode = {
  522. .name = "Hannstar-XGA",
  523. .refresh = 60,
  524. .xres = 1024,
  525. .yres = 768,
  526. .pixclock = 15385,
  527. .left_margin = 220,
  528. .right_margin = 40,
  529. .upper_margin = 21,
  530. .lower_margin = 7,
  531. .hsync_len = 60,
  532. .vsync_len = 10,
  533. .sync = FB_SYNC_EXT,
  534. .vmode = FB_VMODE_NONINTERLACED
  535. } }, {
  536. .bus = 0,
  537. .addr = 0,
  538. .pixfmt = IPU_PIX_FMT_LVDS666,
  539. .detect = NULL,
  540. .enable = enable_lvds,
  541. .mode = {
  542. .name = "LG-9.7",
  543. .refresh = 60,
  544. .xres = 1024,
  545. .yres = 768,
  546. .pixclock = 15385, /* ~65MHz */
  547. .left_margin = 480,
  548. .right_margin = 260,
  549. .upper_margin = 16,
  550. .lower_margin = 6,
  551. .hsync_len = 250,
  552. .vsync_len = 10,
  553. .sync = FB_SYNC_EXT,
  554. .vmode = FB_VMODE_NONINTERLACED
  555. } }, {
  556. .bus = 2,
  557. .addr = 0x38,
  558. .pixfmt = IPU_PIX_FMT_LVDS666,
  559. .detect = detect_i2c,
  560. .enable = enable_lvds,
  561. .mode = {
  562. .name = "wsvga-lvds",
  563. .refresh = 60,
  564. .xres = 1024,
  565. .yres = 600,
  566. .pixclock = 15385,
  567. .left_margin = 220,
  568. .right_margin = 40,
  569. .upper_margin = 21,
  570. .lower_margin = 7,
  571. .hsync_len = 60,
  572. .vsync_len = 10,
  573. .sync = FB_SYNC_EXT,
  574. .vmode = FB_VMODE_NONINTERLACED
  575. } }, {
  576. .bus = 2,
  577. .addr = 0x10,
  578. .pixfmt = IPU_PIX_FMT_RGB666,
  579. .detect = detect_i2c,
  580. .enable = enable_rgb,
  581. .mode = {
  582. .name = "fusion7",
  583. .refresh = 60,
  584. .xres = 800,
  585. .yres = 480,
  586. .pixclock = 33898,
  587. .left_margin = 96,
  588. .right_margin = 24,
  589. .upper_margin = 3,
  590. .lower_margin = 10,
  591. .hsync_len = 72,
  592. .vsync_len = 7,
  593. .sync = 0x40000002,
  594. .vmode = FB_VMODE_NONINTERLACED
  595. } }, {
  596. .bus = 0,
  597. .addr = 0,
  598. .pixfmt = IPU_PIX_FMT_RGB666,
  599. .detect = NULL,
  600. .enable = enable_rgb,
  601. .mode = {
  602. .name = "svga",
  603. .refresh = 60,
  604. .xres = 800,
  605. .yres = 600,
  606. .pixclock = 15385,
  607. .left_margin = 220,
  608. .right_margin = 40,
  609. .upper_margin = 21,
  610. .lower_margin = 7,
  611. .hsync_len = 60,
  612. .vsync_len = 10,
  613. .sync = 0,
  614. .vmode = FB_VMODE_NONINTERLACED
  615. } }, {
  616. .bus = 2,
  617. .addr = 0x41,
  618. .pixfmt = IPU_PIX_FMT_LVDS666,
  619. .detect = detect_i2c,
  620. .enable = enable_lvds,
  621. .mode = {
  622. .name = "amp1024x600",
  623. .refresh = 60,
  624. .xres = 1024,
  625. .yres = 600,
  626. .pixclock = 15385,
  627. .left_margin = 220,
  628. .right_margin = 40,
  629. .upper_margin = 21,
  630. .lower_margin = 7,
  631. .hsync_len = 60,
  632. .vsync_len = 10,
  633. .sync = FB_SYNC_EXT,
  634. .vmode = FB_VMODE_NONINTERLACED
  635. } }, {
  636. .bus = 0,
  637. .addr = 0,
  638. .pixfmt = IPU_PIX_FMT_LVDS666,
  639. .detect = 0,
  640. .enable = enable_lvds,
  641. .mode = {
  642. .name = "wvga-lvds",
  643. .refresh = 57,
  644. .xres = 800,
  645. .yres = 480,
  646. .pixclock = 15385,
  647. .left_margin = 220,
  648. .right_margin = 40,
  649. .upper_margin = 21,
  650. .lower_margin = 7,
  651. .hsync_len = 60,
  652. .vsync_len = 10,
  653. .sync = FB_SYNC_EXT,
  654. .vmode = FB_VMODE_NONINTERLACED
  655. } }, {
  656. .bus = 2,
  657. .addr = 0x48,
  658. .pixfmt = IPU_PIX_FMT_RGB666,
  659. .detect = detect_i2c,
  660. .enable = enable_rgb,
  661. .mode = {
  662. .name = "wvga-rgb",
  663. .refresh = 57,
  664. .xres = 800,
  665. .yres = 480,
  666. .pixclock = 37037,
  667. .left_margin = 40,
  668. .right_margin = 60,
  669. .upper_margin = 10,
  670. .lower_margin = 10,
  671. .hsync_len = 20,
  672. .vsync_len = 10,
  673. .sync = 0,
  674. .vmode = FB_VMODE_NONINTERLACED
  675. } }, {
  676. .bus = 0,
  677. .addr = 0,
  678. .pixfmt = IPU_PIX_FMT_RGB24,
  679. .detect = NULL,
  680. .enable = enable_rgb,
  681. .mode = {
  682. .name = "qvga",
  683. .refresh = 60,
  684. .xres = 320,
  685. .yres = 240,
  686. .pixclock = 37037,
  687. .left_margin = 38,
  688. .right_margin = 37,
  689. .upper_margin = 16,
  690. .lower_margin = 15,
  691. .hsync_len = 30,
  692. .vsync_len = 3,
  693. .sync = 0,
  694. .vmode = FB_VMODE_NONINTERLACED
  695. } } };
  696. size_t display_count = ARRAY_SIZE(displays);
  697. int board_cfb_skip(void)
  698. {
  699. return NULL != env_get("novideo");
  700. }
  701. static void setup_display(void)
  702. {
  703. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  704. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  705. int reg;
  706. enable_ipu_clock();
  707. imx_setup_hdmi();
  708. /* Turn on LDB0,IPU,IPU DI0 clocks */
  709. reg = __raw_readl(&mxc_ccm->CCGR3);
  710. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  711. writel(reg, &mxc_ccm->CCGR3);
  712. /* set LDB0, LDB1 clk select to 011/011 */
  713. reg = readl(&mxc_ccm->cs2cdr);
  714. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  715. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  716. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  717. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  718. writel(reg, &mxc_ccm->cs2cdr);
  719. reg = readl(&mxc_ccm->cscmr2);
  720. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  721. writel(reg, &mxc_ccm->cscmr2);
  722. reg = readl(&mxc_ccm->chsccdr);
  723. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  724. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  725. writel(reg, &mxc_ccm->chsccdr);
  726. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  727. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  728. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  729. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  730. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  731. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  732. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  733. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  734. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  735. writel(reg, &iomux->gpr[2]);
  736. reg = readl(&iomux->gpr[3]);
  737. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  738. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  739. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  740. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  741. writel(reg, &iomux->gpr[3]);
  742. /* backlights off until needed */
  743. SETUP_IOMUX_PADS(backlight_pads);
  744. gpio_direction_input(LVDS_BACKLIGHT_GP);
  745. gpio_direction_input(RGB_BACKLIGHT_GP);
  746. }
  747. #endif
  748. static iomux_v3_cfg_t const init_pads[] = {
  749. /* SGTL5000 sys_mclk */
  750. IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
  751. /* J5 - Camera MCLK */
  752. IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
  753. /* wl1271 pads on nitrogen6x */
  754. /* WL12XX_WL_IRQ_GP */
  755. IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  756. /* WL12XX_WL_ENABLE_GP */
  757. IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  758. /* WL12XX_BT_ENABLE_GP */
  759. IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  760. /* USB otg power */
  761. IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  762. IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
  763. IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
  764. IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
  765. IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
  766. };
  767. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  768. static unsigned gpios_out_low[] = {
  769. /* Disable wl1271 */
  770. IMX_GPIO_NR(6, 15), /* disable wireless */
  771. IMX_GPIO_NR(6, 16), /* disable bluetooth */
  772. IMX_GPIO_NR(3, 22), /* disable USB otg power */
  773. IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
  774. IMX_GPIO_NR(1, 8), /* ov5642 reset */
  775. };
  776. static unsigned gpios_out_high[] = {
  777. IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
  778. IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
  779. };
  780. static void set_gpios(unsigned *p, int cnt, int val)
  781. {
  782. int i;
  783. for (i = 0; i < cnt; i++)
  784. gpio_direction_output(*p++, val);
  785. }
  786. int board_early_init_f(void)
  787. {
  788. setup_iomux_uart();
  789. set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
  790. set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
  791. gpio_direction_input(WL12XX_WL_IRQ_GP);
  792. SETUP_IOMUX_PADS(wl12xx_pads);
  793. SETUP_IOMUX_PADS(init_pads);
  794. setup_buttons();
  795. #if defined(CONFIG_VIDEO_IPUV3)
  796. setup_display();
  797. #endif
  798. return 0;
  799. }
  800. /*
  801. * Do not overwrite the console
  802. * Use always serial for U-Boot console
  803. */
  804. int overwrite_console(void)
  805. {
  806. return 1;
  807. }
  808. int board_init(void)
  809. {
  810. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  811. struct i2c_pads_info *p = i2c_pads;
  812. int i;
  813. int stride = 1;
  814. #if defined(CONFIG_MX6QDL)
  815. stride = 2;
  816. if (!is_mx6dq() && !is_mx6dqp())
  817. p += 1;
  818. #endif
  819. clrsetbits_le32(&iomuxc_regs->gpr[1],
  820. IOMUXC_GPR1_OTG_ID_MASK,
  821. IOMUXC_GPR1_OTG_ID_GPIO1);
  822. SETUP_IOMUX_PADS(misc_pads);
  823. /* address of boot parameters */
  824. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  825. #ifdef CONFIG_MXC_SPI
  826. setup_spi();
  827. #endif
  828. SETUP_IOMUX_PADS(usdhc2_pads);
  829. for (i = 0; i < I2C_BUS_CNT; i++) {
  830. setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
  831. p += stride;
  832. }
  833. #ifdef CONFIG_SATA
  834. setup_sata();
  835. #endif
  836. return 0;
  837. }
  838. int checkboard(void)
  839. {
  840. int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
  841. if (ret < 0) {
  842. /* The gpios have not been probed yet. Read it myself */
  843. struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
  844. int gpio = WL12XX_WL_IRQ_GP & 0x1f;
  845. ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  846. }
  847. if (ret)
  848. puts("Board: Nitrogen6X\n");
  849. else
  850. puts("Board: SABRE Lite\n");
  851. return 0;
  852. }
  853. struct button_key {
  854. char const *name;
  855. unsigned gpnum;
  856. char ident;
  857. };
  858. static struct button_key const buttons[] = {
  859. {"back", IMX_GPIO_NR(2, 2), 'B'},
  860. {"home", IMX_GPIO_NR(2, 4), 'H'},
  861. {"menu", IMX_GPIO_NR(2, 1), 'M'},
  862. {"search", IMX_GPIO_NR(2, 3), 'S'},
  863. {"volup", IMX_GPIO_NR(7, 13), 'V'},
  864. {"voldown", IMX_GPIO_NR(4, 5), 'v'},
  865. };
  866. /*
  867. * generate a null-terminated string containing the buttons pressed
  868. * returns number of keys pressed
  869. */
  870. static int read_keys(char *buf)
  871. {
  872. int i, numpressed = 0;
  873. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  874. if (!gpio_get_value(buttons[i].gpnum))
  875. buf[numpressed++] = buttons[i].ident;
  876. }
  877. buf[numpressed] = '\0';
  878. return numpressed;
  879. }
  880. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  881. {
  882. char envvalue[ARRAY_SIZE(buttons)+1];
  883. int numpressed = read_keys(envvalue);
  884. env_set("keybd", envvalue);
  885. return numpressed == 0;
  886. }
  887. U_BOOT_CMD(
  888. kbd, 1, 1, do_kbd,
  889. "Tests for keypresses, sets 'keybd' environment variable",
  890. "Returns 0 (true) to shell if key is pressed."
  891. );
  892. #ifdef CONFIG_PREBOOT
  893. static char const kbd_magic_prefix[] = "key_magic";
  894. static char const kbd_command_prefix[] = "key_cmd";
  895. static void preboot_keys(void)
  896. {
  897. int numpressed;
  898. char keypress[ARRAY_SIZE(buttons)+1];
  899. numpressed = read_keys(keypress);
  900. if (numpressed) {
  901. char *kbd_magic_keys = env_get("magic_keys");
  902. char *suffix;
  903. /*
  904. * loop over all magic keys
  905. */
  906. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  907. char *keys;
  908. char magic[sizeof(kbd_magic_prefix) + 1];
  909. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  910. keys = env_get(magic);
  911. if (keys) {
  912. if (!strcmp(keys, keypress))
  913. break;
  914. }
  915. }
  916. if (*suffix) {
  917. char cmd_name[sizeof(kbd_command_prefix) + 1];
  918. char *cmd;
  919. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  920. cmd = env_get(cmd_name);
  921. if (cmd) {
  922. env_set("preboot", cmd);
  923. return;
  924. }
  925. }
  926. }
  927. }
  928. #endif
  929. #ifdef CONFIG_CMD_BMODE
  930. static const struct boot_mode board_boot_modes[] = {
  931. /* 4 bit bus width */
  932. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  933. {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  934. {NULL, 0},
  935. };
  936. #endif
  937. int misc_init_r(void)
  938. {
  939. gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
  940. gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
  941. gpio_request(GP_USB_OTG_PWR, "usbotg power");
  942. gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
  943. gpio_request(IMX_GPIO_NR(2, 2), "back");
  944. gpio_request(IMX_GPIO_NR(2, 4), "home");
  945. gpio_request(IMX_GPIO_NR(2, 1), "menu");
  946. gpio_request(IMX_GPIO_NR(2, 3), "search");
  947. gpio_request(IMX_GPIO_NR(7, 13), "volup");
  948. gpio_request(IMX_GPIO_NR(4, 5), "voldown");
  949. #ifdef CONFIG_PREBOOT
  950. preboot_keys();
  951. #endif
  952. #ifdef CONFIG_CMD_BMODE
  953. add_board_boot_modes(board_boot_modes);
  954. #endif
  955. env_set_hex("reset_cause", get_imx_reset_cause());
  956. return 0;
  957. }