clocks.cfg 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013 Boundary Devices
  4. *
  5. * Device Configuration Data (DCD)
  6. *
  7. * Each entry must have the format:
  8. * Addr-type Address Value
  9. *
  10. * where:
  11. * Addr-type register length (1,2 or 4 bytes)
  12. * Address absolute address of the register
  13. * value value to be stored in the register
  14. */
  15. /* set the default clock gate to save power */
  16. DATA 4, CCM_CCGR0, 0x00C03F3F
  17. DATA 4, CCM_CCGR1, 0x0030FC03
  18. DATA 4, CCM_CCGR2, 0x0FFFC000
  19. DATA 4, CCM_CCGR3, 0x3FF00000
  20. DATA 4, CCM_CCGR4, 0x00FFF300
  21. DATA 4, CCM_CCGR5, 0x0F0000C3
  22. DATA 4, CCM_CCGR6, 0x000003FF
  23. /* enable AXI cache for VDOA/VPU/IPU */
  24. DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
  25. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  26. DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
  27. DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
  28. /*
  29. * Setup CCM_CCOSR register as follows:
  30. *
  31. * cko1_en = 1 --> CKO1 enabled
  32. * cko1_div = 111 --> divide by 8
  33. * cko1_sel = 1011 --> ahb_clk_root
  34. *
  35. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  36. */
  37. DATA 4, CCM_CCOSR, 0x000000fb