spl_titanium.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. *
  5. * Based on: gw_ventana_spl.c which is:
  6. * Copyright (C) 2014 Gateworks Corporation
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <spl.h>
  19. #include "platinum.h"
  20. #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  21. /* Configure MX6Q/DUAL mmdc DDR io registers */
  22. struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  23. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  24. .dram_sdclk_0 = 0x00020030,
  25. .dram_sdclk_1 = 0x00020030,
  26. .dram_cas = 0x00020030,
  27. .dram_ras = 0x00020030,
  28. .dram_reset = 0x00020030,
  29. /* SDCKE[0:1]: 100k pull-up */
  30. .dram_sdcke0 = 0x00003000,
  31. .dram_sdcke1 = 0x00003000,
  32. /* SDBA2: pull-up disabled */
  33. .dram_sdba2 = 0x00000000,
  34. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  35. .dram_sdodt0 = 0x00003030,
  36. .dram_sdodt1 = 0x00003030,
  37. /* SDQS[0:7]: Differential input, 40 ohm */
  38. .dram_sdqs0 = 0x00000030,
  39. .dram_sdqs1 = 0x00000030,
  40. .dram_sdqs2 = 0x00000030,
  41. .dram_sdqs3 = 0x00000030,
  42. .dram_sdqs4 = 0x00000030,
  43. .dram_sdqs5 = 0x00000030,
  44. .dram_sdqs6 = 0x00000030,
  45. .dram_sdqs7 = 0x00000030,
  46. /* DQM[0:7]: Differential input, 40 ohm */
  47. .dram_dqm0 = 0x00020030,
  48. .dram_dqm1 = 0x00020030,
  49. .dram_dqm2 = 0x00020030,
  50. .dram_dqm3 = 0x00020030,
  51. .dram_dqm4 = 0x00020030,
  52. .dram_dqm5 = 0x00020030,
  53. .dram_dqm6 = 0x00020030,
  54. .dram_dqm7 = 0x00020030,
  55. };
  56. /* Configure MX6Q/DUAL mmdc GRP io registers */
  57. struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  58. /* DDR3 */
  59. .grp_ddr_type = 0x000c0000,
  60. .grp_ddrmode_ctl = 0x00020000,
  61. /* disable DDR pullups */
  62. .grp_ddrpke = 0x00000000,
  63. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  64. .grp_addds = 0x00000030,
  65. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  66. .grp_ctlds = 0x00000030,
  67. /* DATA[00:63]: Differential input, 40 ohm */
  68. .grp_ddrmode = 0x00020000,
  69. .grp_b0ds = 0x00000030,
  70. .grp_b1ds = 0x00000030,
  71. .grp_b2ds = 0x00000030,
  72. .grp_b3ds = 0x00000030,
  73. .grp_b4ds = 0x00000030,
  74. .grp_b5ds = 0x00000030,
  75. .grp_b6ds = 0x00000030,
  76. .grp_b7ds = 0x00000030,
  77. };
  78. /* MT41J128M16JT-125 */
  79. static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
  80. .mem_speed = 1600,
  81. .density = 2,
  82. .width = 16,
  83. .banks = 8,
  84. .rowaddr = 14,
  85. .coladdr = 10,
  86. .pagesz = 2,
  87. .trcd = 1375,
  88. .trcmin = 4875,
  89. .trasmin = 3500,
  90. };
  91. static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
  92. /* Write leveling calibration determine */
  93. .p0_mpwldectrl0 = 0x001f001f,
  94. .p0_mpwldectrl1 = 0x001f001f,
  95. .p1_mpwldectrl0 = 0x00440044,
  96. .p1_mpwldectrl1 = 0x00440044,
  97. /* Read DQS Gating calibration */
  98. .p0_mpdgctrl0 = 0x434b0350,
  99. .p0_mpdgctrl1 = 0x034c0359,
  100. .p1_mpdgctrl0 = 0x434b0350,
  101. .p1_mpdgctrl1 = 0x03650348,
  102. /* Read Calibration: DQS delay relative to DQ read access */
  103. .p0_mprddlctl = 0x4436383b,
  104. .p1_mprddlctl = 0x39393341,
  105. /* Write Calibration: DQ/DM delay relative to DQS write access */
  106. .p0_mpwrdlctl = 0x35373933,
  107. .p1_mpwrdlctl = 0x48254a36,
  108. };
  109. static void spl_dram_init(int width)
  110. {
  111. struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
  112. struct mx6_ddr_sysinfo sysinfo = {
  113. /* width of data bus:0=16,1=32,2=64 */
  114. .dsize = width / 32,
  115. /* config for full 4GB range so that get_mem_size() works */
  116. .cs_density = 32, /* 32Gb per CS */
  117. /* single chip select */
  118. .ncs = 1,
  119. .cs1_mirror = 1,
  120. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  121. #ifdef RTT_NOM_120OHM
  122. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  123. #else
  124. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  125. #endif
  126. .walat = 0, /* Write additional latency */
  127. .ralat = 5, /* Read additional latency */
  128. .mif3_mode = 3, /* Command prediction working mode */
  129. .bi_on = 1, /* Bank interleaving enabled */
  130. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  131. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  132. .ddr_type = DDR_TYPE_DDR3,
  133. .refsel = 1, /* Refresh cycles at 32KHz */
  134. .refr = 7, /* 8 refresh commands per refresh cycle */
  135. };
  136. mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  137. mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
  138. }
  139. /*
  140. * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  141. * - we have a stack and a place to store GD, both in SRAM
  142. * - no variable global data is available
  143. */
  144. void board_init_f(ulong dummy)
  145. {
  146. /* Setup AIPS and disable watchdog */
  147. arch_cpu_init();
  148. ccgr_init();
  149. gpr_init();
  150. /* UART iomux */
  151. board_early_init_f();
  152. /* Setup GP timer */
  153. timer_init();
  154. /* UART clocks enabled and gd valid - init serial console */
  155. preloader_console_init();
  156. /* Init DDR with 32bit width */
  157. spl_dram_init(32);
  158. /* Clear the BSS */
  159. memset(__bss_start, 0, __bss_end - __bss_start);
  160. /*
  161. * Setup enet related MUXing early to give the PHY
  162. * some time to wake-up from reset
  163. */
  164. platinum_setup_enet();
  165. /* load/boot image from boot device */
  166. board_init_r(NULL, 0);
  167. }