platinum_picon.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Barco (www.barco.com)
  4. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  5. */
  6. #include <common.h>
  7. #include <asm/gpio.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/mach-imx/mxc_i2c.h>
  14. #include <i2c.h>
  15. #include <miiphy.h>
  16. #include "platinum.h"
  17. #define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18)
  18. #define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13)
  19. #define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19)
  20. #define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2)
  21. #define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11)
  22. #define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13)
  23. #define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17)
  24. #define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20)
  25. #define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14)
  26. #define GPIO_USB_RESET IMX_GPIO_NR(1, 5)
  27. iomux_v3_cfg_t const ecspi1_pads[] = {
  28. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
  29. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  30. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  31. MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  32. MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  33. MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  34. };
  35. iomux_v3_cfg_t const ecspi2_pads[] = {
  36. MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
  37. MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  38. MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  39. MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  40. MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  41. };
  42. iomux_v3_cfg_t const enet_pads[] = {
  43. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  44. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  45. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  46. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  47. MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  48. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  49. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  50. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  51. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  52. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53. };
  54. /* PHY nRESET */
  55. iomux_v3_cfg_t const phy_reset_pad = {
  56. MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  57. };
  58. iomux_v3_cfg_t const uart1_pads[] = {
  59. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. };
  62. iomux_v3_cfg_t const uart4_pads[] = {
  63. MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  66. MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  67. };
  68. iomux_v3_cfg_t const uart5_pads[] = {
  69. MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  71. MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  72. MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. };
  74. iomux_v3_cfg_t const i2c0_mux_pads[] = {
  75. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  76. MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  77. MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  78. };
  79. iomux_v3_cfg_t const i2c2_mux_pads[] = {
  80. MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  81. MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  82. MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  83. };
  84. struct i2c_pads_info i2c_pad_info0 = {
  85. .scl = {
  86. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
  87. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
  88. .gp = IMX_GPIO_NR(5, 27)
  89. },
  90. .sda = {
  91. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  92. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  93. .gp = IMX_GPIO_NR(5, 26)
  94. }
  95. };
  96. struct i2c_pads_info i2c_pad_info2 = {
  97. .scl = {
  98. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
  99. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
  100. .gp = IMX_GPIO_NR(1, 3)
  101. },
  102. .sda = {
  103. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  104. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  105. .gp = IMX_GPIO_NR(1, 6)
  106. }
  107. };
  108. /*
  109. * This enet related pin-muxing and GPIO handling is done
  110. * in SPL U-Boot. For early initialization. And to give the
  111. * PHY some time to come out of reset before the U-Boot
  112. * ethernet driver tries to access its registers via MDIO.
  113. */
  114. int platinum_setup_enet(void)
  115. {
  116. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  117. unsigned phy_reset = IMX_GPIO_NR(1, 19);
  118. /* First configure PHY reset GPIO pin */
  119. imx_iomux_v3_setup_pad(phy_reset_pad);
  120. /* Reconfigure enet muxing while PHY is in reset */
  121. gpio_direction_output(phy_reset, 0);
  122. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  123. mdelay(10);
  124. gpio_set_value(phy_reset, 1);
  125. udelay(100);
  126. /* set GPIO_16 as ENET_REF_CLK_OUT */
  127. setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  128. return enable_fec_anatop_clock(0, ENET_50MHZ);
  129. }
  130. int platinum_setup_i2c(void)
  131. {
  132. imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
  133. ARRAY_SIZE(i2c0_mux_pads));
  134. imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
  135. ARRAY_SIZE(i2c2_mux_pads));
  136. mdelay(10);
  137. /* Disable i2c mux 0 */
  138. gpio_direction_output(GPIO_I2C0_SEL0, 0);
  139. gpio_direction_output(GPIO_I2C0_SEL1, 0);
  140. gpio_direction_output(GPIO_I2C0_ENBN, 1);
  141. /* Disable i2c mux 1 */
  142. gpio_direction_output(GPIO_I2C2_SEL0, 0);
  143. gpio_direction_output(GPIO_I2C2_SEL1, 0);
  144. gpio_direction_output(GPIO_I2C2_ENBN, 1);
  145. udelay(10);
  146. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  147. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  148. /* Disable all leds */
  149. i2c_set_bus_num(0);
  150. i2c_reg_write(0x60, 0x05, 0x55);
  151. return 0;
  152. }
  153. int platinum_setup_spi(void)
  154. {
  155. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  156. imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
  157. return 0;
  158. }
  159. int platinum_setup_uart(void)
  160. {
  161. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  162. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  163. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  164. return 0;
  165. }
  166. int platinum_phy_config(struct phy_device *phydev)
  167. {
  168. /* Use generic infrastructure, no specific setup */
  169. if (phydev->drv->config)
  170. phydev->drv->config(phydev);
  171. return 0;
  172. }
  173. int platinum_init_gpio(void)
  174. {
  175. /* Reset FPGA's */
  176. gpio_direction_output(GPIO_IP_NCONFIG, 0);
  177. gpio_direction_output(GPIO_HK_NCONFIG, 0);
  178. gpio_direction_output(GPIO_LS_NCONFIG, 0);
  179. udelay(3);
  180. gpio_set_value(GPIO_IP_NCONFIG, 1);
  181. gpio_set_value(GPIO_HK_NCONFIG, 1);
  182. gpio_set_value(GPIO_LS_NCONFIG, 1);
  183. /* no dmd configuration yet */
  184. return 0;
  185. }
  186. int platinum_init_usb(void)
  187. {
  188. /* Reset usb hub */
  189. gpio_direction_output(GPIO_USB_RESET, 0);
  190. udelay(100);
  191. gpio_set_value(GPIO_USB_RESET, 1);
  192. return 0;
  193. }
  194. int platinum_init_finished(void)
  195. {
  196. /* Enable led 0 */
  197. i2c_set_bus_num(0);
  198. i2c_reg_write(0x60, 0x05, 0x54);
  199. return 0;
  200. }