fpga.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002-2013
  4. * Eric Jarrige <eric.jarrige@armadeus.org>
  5. *
  6. * based on the files by
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com
  8. * and
  9. * Keith Outwater, keith_outwater@mvis.com
  10. */
  11. #include <common.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <command.h>
  16. #include <config.h>
  17. #include "fpga.h"
  18. #include <spartan3.h>
  19. #include "apf27.h"
  20. /*
  21. * Note that these are pointers to code that is in Flash. They will be
  22. * relocated at runtime.
  23. * Spartan2 code is used to download our Spartan 3 :) code is compatible.
  24. * Just take care about the file size
  25. */
  26. xilinx_spartan3_slave_parallel_fns fpga_fns = {
  27. fpga_pre_fn,
  28. fpga_pgm_fn,
  29. fpga_init_fn,
  30. NULL,
  31. fpga_done_fn,
  32. fpga_clk_fn,
  33. fpga_cs_fn,
  34. fpga_wr_fn,
  35. fpga_rdata_fn,
  36. fpga_wdata_fn,
  37. fpga_busy_fn,
  38. fpga_abort_fn,
  39. fpga_post_fn,
  40. };
  41. xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  42. {xilinx_spartan3,
  43. slave_parallel,
  44. 1196128l/8,
  45. (void *)&fpga_fns,
  46. 0,
  47. &spartan3_op,
  48. "3s200aft256"}
  49. };
  50. /*
  51. * Initialize GPIO port B before download
  52. */
  53. int fpga_pre_fn(int cookie)
  54. {
  55. /* Initialize GPIO pins */
  56. gpio_set_value(ACFG_FPGA_PWR, 1);
  57. imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
  58. imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
  59. imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  60. imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  61. imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  62. imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  63. imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
  64. gpio_set_value(ACFG_FPGA_RESET, 1);
  65. imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  66. imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  67. gpio_set_value(ACFG_FPGA_PRG, 1);
  68. gpio_set_value(ACFG_FPGA_CLK, 1);
  69. gpio_set_value(ACFG_FPGA_RW, 1);
  70. gpio_set_value(ACFG_FPGA_CS, 1);
  71. gpio_set_value(ACFG_FPGA_SUSPEND, 0);
  72. gpio_set_value(ACFG_FPGA_PWR, 0);
  73. udelay(30000); /*wait until supply started*/
  74. return cookie;
  75. }
  76. /*
  77. * Set the FPGA's active-low program line to the specified level
  78. */
  79. int fpga_pgm_fn(int assert, int flush, int cookie)
  80. {
  81. debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
  82. assert ? "high" : "low");
  83. gpio_set_value(ACFG_FPGA_PRG, !assert);
  84. return assert;
  85. }
  86. /*
  87. * Set the FPGA's active-high clock line to the specified level
  88. */
  89. int fpga_clk_fn(int assert_clk, int flush, int cookie)
  90. {
  91. debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
  92. assert_clk ? "high" : "low");
  93. gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
  94. return assert_clk;
  95. }
  96. /*
  97. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  98. * asserted (low).
  99. */
  100. int fpga_init_fn(int cookie)
  101. {
  102. int value;
  103. debug("%s:%d: INIT check... ", __func__, __LINE__);
  104. value = gpio_get_value(ACFG_FPGA_INIT);
  105. /* printf("init value read %x",value); */
  106. #ifdef CONFIG_SYS_FPGA_IS_PROTO
  107. return value;
  108. #else
  109. return !value;
  110. #endif
  111. }
  112. /*
  113. * Test the state of the active-high FPGA DONE pin
  114. */
  115. int fpga_done_fn(int cookie)
  116. {
  117. debug("%s:%d: DONE check... %s", __func__, __LINE__,
  118. gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
  119. return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
  120. }
  121. /*
  122. * Set the FPGA's wr line to the specified level
  123. */
  124. int fpga_wr_fn(int assert_write, int flush, int cookie)
  125. {
  126. debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
  127. assert_write ? "high" : "low");
  128. gpio_set_value(ACFG_FPGA_RW, !assert_write);
  129. return assert_write;
  130. }
  131. int fpga_cs_fn(int assert_cs, int flush, int cookie)
  132. {
  133. debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
  134. assert_cs ? "high" : "low");
  135. gpio_set_value(ACFG_FPGA_CS, !assert_cs);
  136. return assert_cs;
  137. }
  138. int fpga_rdata_fn(unsigned char *data, int cookie)
  139. {
  140. debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
  141. *((char *)ACFG_FPGA_RDATA));
  142. *data = (unsigned char)
  143. ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
  144. return *data;
  145. }
  146. int fpga_wdata_fn(unsigned char data, int flush, int cookie)
  147. {
  148. debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
  149. data);
  150. *((unsigned short *)ACFG_FPGA_WDATA) = data;
  151. return data;
  152. }
  153. int fpga_abort_fn(int cookie)
  154. {
  155. return fpga_post_fn(cookie);
  156. }
  157. int fpga_busy_fn(int cookie)
  158. {
  159. return 1;
  160. }
  161. int fpga_post_fn(int cookie)
  162. {
  163. debug("%s:%d: FPGA POST ", __func__, __LINE__);
  164. imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
  165. imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
  166. imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
  167. gpio_set_value(ACFG_FPGA_PRG, 1);
  168. gpio_set_value(ACFG_FPGA_RESET, 0);
  169. imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
  170. return cookie;
  171. }
  172. void apf27_fpga_setup(void)
  173. {
  174. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  175. struct system_control_regs *system =
  176. (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
  177. /* Configure FPGA CLKO */
  178. writel(ACFG_CCSR_VAL, &pll->ccsr);
  179. /* Configure strentgh for FPGA */
  180. writel(ACFG_DSCR10_VAL, &system->dscr10);
  181. writel(ACFG_DSCR3_VAL, &system->dscr3);
  182. writel(ACFG_DSCR7_VAL, &system->dscr7);
  183. writel(ACFG_DSCR2_VAL, &system->dscr2);
  184. }
  185. /*
  186. * Initialize the fpga. Return 1 on success, 0 on failure.
  187. */
  188. void APF27_init_fpga(void)
  189. {
  190. int i;
  191. apf27_fpga_setup();
  192. fpga_init();
  193. for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
  194. debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
  195. fpga_add(fpga_xilinx, &fpga[i]);
  196. }
  197. return;
  198. }