apf27.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
  4. *
  5. * based on the files by
  6. * Sascha Hauer, Pengutronix
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <jffs2/jffs2.h>
  11. #include <nand.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/gpio.h>
  17. #include <linux/errno.h>
  18. #include <u-boot/crc.h>
  19. #include "apf27.h"
  20. #include "fpga.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /*
  23. * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
  24. * customer use. The APF27 board uses this fuse to store the board revision:
  25. * 0: initial board revision
  26. * 1: first revision - Presence of the second RAM chip on the board is blown in
  27. * fuse bank 1 row 9 bit 0 - No hardware change
  28. * N: to be defined
  29. */
  30. static u32 get_board_rev(void)
  31. {
  32. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  33. return readl(&iim->bank[1].fuse_regs[8]);
  34. }
  35. /*
  36. * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
  37. * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
  38. * the presence of the second RAM chip
  39. * 0: AFP27 with 1 RAM of 64 MiB
  40. * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
  41. */
  42. static int get_num_ram_bank(void)
  43. {
  44. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  45. int nr_dram_banks = 1;
  46. if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
  47. nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
  48. else
  49. nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
  50. return nr_dram_banks;
  51. }
  52. static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
  53. u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
  54. u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
  55. u32 puen, u32 gius)
  56. {
  57. struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
  58. writel(gpio_dr, &regs->port[port].gpio_dr);
  59. writel(ocr1, &regs->port[port].ocr1);
  60. writel(ocr2, &regs->port[port].ocr2);
  61. writel(iconfa1, &regs->port[port].iconfa1);
  62. writel(iconfa2, &regs->port[port].iconfa2);
  63. writel(iconfb1, &regs->port[port].iconfb1);
  64. writel(iconfb2, &regs->port[port].iconfb2);
  65. writel(icr1, &regs->port[port].icr1);
  66. writel(icr2, &regs->port[port].icr2);
  67. writel(imr, &regs->port[port].imr);
  68. writel(gpio_dir, &regs->port[port].gpio_dir);
  69. writel(gpr, &regs->port[port].gpr);
  70. writel(puen, &regs->port[port].puen);
  71. writel(gius, &regs->port[port].gius);
  72. }
  73. #define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
  74. ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
  75. ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
  76. ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
  77. ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
  78. ACFG_GIUS_##n##_VAL)
  79. static void apf27_iomux_init(void)
  80. {
  81. APF27_PORT_INIT(A);
  82. APF27_PORT_INIT(B);
  83. APF27_PORT_INIT(C);
  84. APF27_PORT_INIT(D);
  85. APF27_PORT_INIT(E);
  86. APF27_PORT_INIT(F);
  87. }
  88. static int apf27_devices_init(void)
  89. {
  90. int i;
  91. unsigned int mode[] = {
  92. PC5_PF_I2C2_DATA,
  93. PC6_PF_I2C2_CLK,
  94. PD17_PF_I2C_DATA,
  95. PD18_PF_I2C_CLK,
  96. };
  97. for (i = 0; i < ARRAY_SIZE(mode); i++)
  98. imx_gpio_mode(mode[i]);
  99. #ifdef CONFIG_MXC_UART
  100. mx27_uart1_init_pins();
  101. #endif
  102. #ifdef CONFIG_FEC_MXC
  103. mx27_fec_init_pins();
  104. #endif
  105. #ifdef CONFIG_MMC_MXC
  106. mx27_sd2_init_pins();
  107. imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
  108. gpio_request(PC_PWRON, "pc_pwron");
  109. gpio_set_value(PC_PWRON, 1);
  110. #endif
  111. return 0;
  112. }
  113. static void apf27_setup_csx(void)
  114. {
  115. struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
  116. writel(ACFG_CS0U_VAL, &weim->cs0u);
  117. writel(ACFG_CS0L_VAL, &weim->cs0l);
  118. writel(ACFG_CS0A_VAL, &weim->cs0a);
  119. writel(ACFG_CS1U_VAL, &weim->cs1u);
  120. writel(ACFG_CS1L_VAL, &weim->cs1l);
  121. writel(ACFG_CS1A_VAL, &weim->cs1a);
  122. writel(ACFG_CS2U_VAL, &weim->cs2u);
  123. writel(ACFG_CS2L_VAL, &weim->cs2l);
  124. writel(ACFG_CS2A_VAL, &weim->cs2a);
  125. writel(ACFG_CS3U_VAL, &weim->cs3u);
  126. writel(ACFG_CS3L_VAL, &weim->cs3l);
  127. writel(ACFG_CS3A_VAL, &weim->cs3a);
  128. writel(ACFG_CS4U_VAL, &weim->cs4u);
  129. writel(ACFG_CS4L_VAL, &weim->cs4l);
  130. writel(ACFG_CS4A_VAL, &weim->cs4a);
  131. writel(ACFG_CS5U_VAL, &weim->cs5u);
  132. writel(ACFG_CS5L_VAL, &weim->cs5l);
  133. writel(ACFG_CS5A_VAL, &weim->cs5a);
  134. writel(ACFG_EIM_VAL, &weim->eim);
  135. }
  136. static void apf27_setup_port(void)
  137. {
  138. struct system_control_regs *system =
  139. (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
  140. writel(ACFG_FMCR_VAL, &system->fmcr);
  141. }
  142. int board_init(void)
  143. {
  144. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  145. apf27_setup_csx();
  146. apf27_setup_port();
  147. apf27_iomux_init();
  148. apf27_devices_init();
  149. #if defined(CONFIG_FPGA)
  150. APF27_init_fpga();
  151. #endif
  152. return 0;
  153. }
  154. int dram_init(void)
  155. {
  156. gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  157. if (get_num_ram_bank() > 1)
  158. gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
  159. PHYS_SDRAM_2_SIZE);
  160. return 0;
  161. }
  162. int dram_init_banksize(void)
  163. {
  164. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  165. gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
  166. PHYS_SDRAM_1_SIZE);
  167. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  168. if (get_num_ram_bank() > 1)
  169. gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
  170. PHYS_SDRAM_2_SIZE);
  171. else
  172. gd->bd->bi_dram[1].size = 0;
  173. return 0;
  174. }
  175. ulong board_get_usable_ram_top(ulong total_size)
  176. {
  177. ulong ramtop;
  178. if (get_num_ram_bank() > 1)
  179. ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
  180. PHYS_SDRAM_2_SIZE);
  181. else
  182. ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
  183. PHYS_SDRAM_1_SIZE);
  184. return ramtop;
  185. }
  186. int checkboard(void)
  187. {
  188. printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
  189. return 0;
  190. }
  191. #ifdef CONFIG_SPL_BUILD
  192. inline void hang(void)
  193. {
  194. for (;;)
  195. ;
  196. }
  197. void board_init_f(ulong bootflag)
  198. {
  199. /*
  200. * copy ourselves from where we are running to where we were
  201. * linked at. Use ulong pointers as all addresses involved
  202. * are 4-byte-aligned.
  203. */
  204. ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
  205. asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
  206. asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
  207. asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
  208. asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
  209. for (dst = start_ptr; dst < end_ptr; dst++)
  210. *dst = *(dst+(run_ptr-link_ptr));
  211. /*
  212. * branch to nand_boot's link-time address.
  213. */
  214. asm volatile("ldr pc, =nand_boot");
  215. }
  216. #endif /* CONFIG_SPL_BUILD */