mt41j128M.cfg 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013 Boundary Devices
  4. */
  5. /* ZQ Calibration */
  6. DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
  7. DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
  8. DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
  9. DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
  10. DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
  11. DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
  12. /*
  13. * DQS gating, read delay, write delay calibration values
  14. * based on calibration compare of 0x00ffff00
  15. */
  16. DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
  17. DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
  18. DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
  19. DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
  20. DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
  21. DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
  22. DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
  23. DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
  24. /* read data bit delay */
  25. DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
  26. DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
  27. DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
  28. DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
  29. DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
  30. DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
  31. DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
  32. DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
  33. /* Complete calibration by forced measurment */
  34. DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
  35. DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
  36. /* in DDR3, 64-bit mode, only MMDC0 is initiated */
  37. DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
  38. DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
  39. DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
  40. DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
  41. DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
  42. DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
  43. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
  44. DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
  45. DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
  46. DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
  47. DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
  48. /* MR2 */
  49. DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
  50. DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
  51. /* MR3 */
  52. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
  53. DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
  54. /* MR1 */
  55. DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
  56. DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
  57. /* MR0 */
  58. DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
  59. DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
  60. /* ZQ calibration */
  61. DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
  62. DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
  63. /* final ddr setup */
  64. DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
  65. DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
  66. DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
  67. DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
  68. DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
  69. DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000