aristainetos.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  8. *
  9. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10. */
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/mach-imx/video.h>
  21. #include <mmc.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <miiphy.h>
  24. #include <netdev.h>
  25. #include <asm/arch/mxc_hdmi.h>
  26. #include <asm/arch/crm_regs.h>
  27. #include <linux/fb.h>
  28. #include <ipu_pixfmt.h>
  29. #include <input.h>
  30. #include <asm/io.h>
  31. #include <asm/arch/sys_proto.h>
  32. #include <pwm.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  35. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  38. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  41. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  43. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  44. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  46. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  48. #define DISP_PAD_CTRL (0x10)
  49. #define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
  50. #if (CONFIG_SYS_BOARD_VERSION == 1)
  51. #include "./aristainetos-v1.c"
  52. #elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
  53. #include "./aristainetos-v2.c"
  54. #endif
  55. struct i2c_pads_info i2c_pad_info1 = {
  56. .scl = {
  57. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  58. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  59. .gp = IMX_GPIO_NR(5, 27)
  60. },
  61. .sda = {
  62. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  63. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  64. .gp = IMX_GPIO_NR(5, 26)
  65. }
  66. };
  67. struct i2c_pads_info i2c_pad_info2 = {
  68. .scl = {
  69. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  70. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  71. .gp = IMX_GPIO_NR(4, 12)
  72. },
  73. .sda = {
  74. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  75. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  76. .gp = IMX_GPIO_NR(4, 13)
  77. }
  78. };
  79. iomux_v3_cfg_t const usdhc1_pads[] = {
  80. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86. };
  87. int dram_init(void)
  88. {
  89. gd->ram_size = imx_ddr_size();
  90. return 0;
  91. }
  92. #ifdef CONFIG_FSL_ESDHC_IMX
  93. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  94. {USDHC1_BASE_ADDR},
  95. {USDHC2_BASE_ADDR},
  96. };
  97. int board_mmc_getcd(struct mmc *mmc)
  98. {
  99. return 1;
  100. }
  101. int board_mmc_init(bd_t *bis)
  102. {
  103. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  104. imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  105. #if (CONFIG_SYS_BOARD_VERSION == 2)
  106. /*
  107. * usdhc2 has a levelshifter on the carrier board Rev. DV1,
  108. * that will automatically detect the driving direction.
  109. * During initialisation this isn't working correctly,
  110. * which causes DAT3 to be driven low towards the SD-card.
  111. * This causes a SD-card enetring the SPI-Mode
  112. * and therefore getting inaccessible until next power cycle.
  113. * As workaround we drive the DAT3 line as GPIO and set it high.
  114. * This makes usdhc2 unusable in u-boot, but works for the
  115. * initialisation in Linux
  116. */
  117. imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
  118. MUX_PAD_CTRL(NO_PAD_CTRL));
  119. gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
  120. #endif
  121. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  122. }
  123. #endif
  124. /*
  125. * Do not overwrite the console
  126. * Use always serial for U-Boot console
  127. */
  128. int overwrite_console(void)
  129. {
  130. return 1;
  131. }
  132. struct display_info_t const displays[] = {
  133. {
  134. .bus = -1,
  135. .addr = 0,
  136. .pixfmt = IPU_PIX_FMT_RGB24,
  137. .detect = NULL,
  138. .enable = enable_lvds,
  139. .mode = {
  140. .name = "lb07wv8",
  141. .refresh = 60,
  142. .xres = 800,
  143. .yres = 480,
  144. .pixclock = 30066,
  145. .left_margin = 88,
  146. .right_margin = 88,
  147. .upper_margin = 20,
  148. .lower_margin = 20,
  149. .hsync_len = 80,
  150. .vsync_len = 5,
  151. .sync = FB_SYNC_EXT,
  152. .vmode = FB_VMODE_NONINTERLACED
  153. }
  154. }
  155. #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
  156. , {
  157. .bus = -1,
  158. .addr = 0,
  159. .pixfmt = IPU_PIX_FMT_RGB24,
  160. .detect = NULL,
  161. .enable = enable_spi_display,
  162. .mode = {
  163. .name = "lg4573",
  164. .refresh = 57,
  165. .xres = 480,
  166. .yres = 800,
  167. .pixclock = 37037,
  168. .left_margin = 59,
  169. .right_margin = 10,
  170. .upper_margin = 15,
  171. .lower_margin = 15,
  172. .hsync_len = 10,
  173. .vsync_len = 15,
  174. .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
  175. FB_SYNC_VERT_HIGH_ACT,
  176. .vmode = FB_VMODE_NONINTERLACED
  177. }
  178. }
  179. #endif
  180. };
  181. size_t display_count = ARRAY_SIZE(displays);
  182. /* no console on this board */
  183. int board_cfb_skip(void)
  184. {
  185. return 1;
  186. }
  187. iomux_v3_cfg_t nfc_pads[] = {
  188. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  189. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  190. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  191. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  192. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  193. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  194. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  195. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  196. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  197. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  198. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  199. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  200. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  201. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  202. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  203. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  204. };
  205. static void setup_gpmi_nand(void)
  206. {
  207. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  208. /* config gpmi nand iomux */
  209. imx_iomux_v3_setup_multiple_pads(nfc_pads,
  210. ARRAY_SIZE(nfc_pads));
  211. /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  212. clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  213. /* config gpmi and bch clock to 100 MHz */
  214. clrsetbits_le32(&mxc_ccm->cs2cdr,
  215. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  216. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  217. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  218. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  219. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  220. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  221. /* enable ENFC_CLK_ROOT clock */
  222. setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  223. /* enable gpmi and bch clock gating */
  224. setbits_le32(&mxc_ccm->CCGR4,
  225. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  226. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  227. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  228. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  229. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  230. /* enable apbh clock gating */
  231. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  232. }
  233. int board_init(void)
  234. {
  235. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  236. /* address of boot parameters */
  237. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  238. setup_spi();
  239. setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  240. &i2c_pad_info1);
  241. setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  242. &i2c_pad_info2);
  243. setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  244. &i2c_pad_info3);
  245. setup_i2c4();
  246. /* SPI NOR Flash read only */
  247. gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
  248. gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
  249. gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
  250. setup_board_gpio();
  251. setup_gpmi_nand();
  252. setup_board_spi();
  253. /* GPIO_1 for USB_OTG_ID */
  254. clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
  255. imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
  256. return 0;
  257. }
  258. int checkboard(void)
  259. {
  260. printf("Board: %s\n", CONFIG_BOARDNAME);
  261. return 0;
  262. }
  263. #ifdef CONFIG_USB_EHCI_MX6
  264. int board_ehci_hcd_init(int port)
  265. {
  266. int ret;
  267. ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
  268. if (!ret)
  269. gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
  270. ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
  271. if (!ret)
  272. gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
  273. return 0;
  274. }
  275. int board_ehci_power(int port, int on)
  276. {
  277. if (port)
  278. gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
  279. else
  280. gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
  281. return 0;
  282. }
  283. #endif