aristainetos-v1.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  8. *
  9. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10. */
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/mach-imx/video.h>
  21. #include <mmc.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <miiphy.h>
  24. #include <netdev.h>
  25. #include <asm/arch/mxc_hdmi.h>
  26. #include <asm/arch/crm_regs.h>
  27. #include <linux/fb.h>
  28. #include <ipu_pixfmt.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <pwm.h>
  32. struct i2c_pads_info i2c_pad_info3 = {
  33. .scl = {
  34. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  35. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  36. .gp = IMX_GPIO_NR(3, 17)
  37. },
  38. .sda = {
  39. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  40. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  41. .gp = IMX_GPIO_NR(3, 18)
  42. }
  43. };
  44. iomux_v3_cfg_t const uart1_pads[] = {
  45. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  46. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. };
  48. iomux_v3_cfg_t const uart5_pads[] = {
  49. MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. };
  52. iomux_v3_cfg_t const gpio_pads[] = {
  53. /* LED enable */
  54. MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  55. /* spi flash WP protect */
  56. MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  57. /* backlight enable */
  58. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  59. /* LED yellow */
  60. MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  61. /* LED red */
  62. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  63. /* LED green */
  64. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  65. /* LED blue */
  66. MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  67. /* i2c4 scl */
  68. MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  69. /* i2c4 sda */
  70. MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71. /* spi CS 1 */
  72. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  73. };
  74. static iomux_v3_cfg_t const misc_pads[] = {
  75. MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  76. /* OTG Power enable */
  77. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
  78. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  79. };
  80. iomux_v3_cfg_t const enet_pads[] = {
  81. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
  82. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87. MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. };
  92. static void setup_iomux_enet(void)
  93. {
  94. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  95. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  96. /* set GPIO_16 as ENET_REF_CLK_OUT */
  97. setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  98. }
  99. static iomux_v3_cfg_t const backlight_pads[] = {
  100. MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  101. MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  103. };
  104. iomux_v3_cfg_t const ecspi4_pads[] = {
  105. MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
  107. MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
  108. MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  109. };
  110. static iomux_v3_cfg_t const display_pads[] = {
  111. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
  112. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  113. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  114. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  115. MX6_PAD_DI0_PIN4__GPIO4_IO20,
  116. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  117. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  118. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  119. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  120. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  121. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  122. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  123. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  124. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  125. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  126. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  127. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  128. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  129. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  130. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  131. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  132. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  133. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  134. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  135. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  136. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  137. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  138. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  139. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  140. };
  141. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  142. {
  143. return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
  144. ? (IMX_GPIO_NR(3, 20)) : -1;
  145. }
  146. static void setup_spi(void)
  147. {
  148. int i;
  149. imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
  150. for (i = 0; i < 3; i++)
  151. enable_spi_clk(true, i);
  152. /* set cs1 to high */
  153. gpio_direction_output(ECSPI4_CS1, 1);
  154. }
  155. static void setup_iomux_uart(void)
  156. {
  157. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  158. }
  159. int board_eth_init(bd_t *bis)
  160. {
  161. struct iomuxc *iomuxc_regs =
  162. (struct iomuxc *)IOMUXC_BASE_ADDR;
  163. int ret;
  164. /* clear gpr1[14], gpr1[18:17] to select anatop clock */
  165. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
  166. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  167. if (ret)
  168. return ret;
  169. setup_iomux_enet();
  170. return cpu_eth_init(bis);
  171. }
  172. static void enable_lvds(struct display_info_t const *dev)
  173. {
  174. imx_iomux_v3_setup_multiple_pads(
  175. display_pads,
  176. ARRAY_SIZE(display_pads));
  177. imx_iomux_v3_setup_multiple_pads(
  178. backlight_pads,
  179. ARRAY_SIZE(backlight_pads));
  180. /* enable backlight PWM 3 */
  181. if (pwm_init(2, 0, 0))
  182. goto error;
  183. /* duty cycle 500ns, period: 3000ns */
  184. if (pwm_config(2, 500, 3000))
  185. goto error;
  186. if (pwm_enable(2))
  187. goto error;
  188. return;
  189. error:
  190. puts("error init pwm for backlight\n");
  191. return;
  192. }
  193. static void setup_display(void)
  194. {
  195. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  196. int reg;
  197. enable_ipu_clock();
  198. reg = readl(&mxc_ccm->cs2cdr);
  199. /* select pll 5 clock */
  200. reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
  201. reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
  202. writel(reg, &mxc_ccm->cs2cdr);
  203. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  204. ARRAY_SIZE(backlight_pads));
  205. }
  206. static void setup_iomux_gpio(void)
  207. {
  208. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  209. }
  210. int board_early_init_f(void)
  211. {
  212. setup_iomux_uart();
  213. setup_iomux_gpio();
  214. setup_display();
  215. return 0;
  216. }
  217. static void setup_i2c4(void)
  218. {
  219. /* i2c4 not used, set it to gpio input */
  220. gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
  221. gpio_direction_input(IMX_GPIO_NR(1, 7));
  222. gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
  223. gpio_direction_input(IMX_GPIO_NR(1, 8));
  224. }
  225. static void setup_board_gpio(void)
  226. {
  227. /* enable LED */
  228. gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
  229. gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
  230. gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
  231. gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
  232. gpio_request(IMX_GPIO_NR(1, 4), "LED red");
  233. gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
  234. gpio_request(IMX_GPIO_NR(1, 5), "LED green");
  235. gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
  236. gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
  237. gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
  238. }
  239. static void setup_board_spi(void)
  240. {
  241. }