spl.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <spl.h>
  8. #include <fsl_esdhc.h>
  9. #include <asm/io.h>
  10. #include <asm/gpio.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sci/sci.h>
  13. #include <asm/arch/imx8-pins.h>
  14. #include <asm/arch/iomux.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  17. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  18. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  19. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  20. #define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  21. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  22. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  23. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  24. #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
  25. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  26. (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  27. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  28. #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  29. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  30. (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  31. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  32. #define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  33. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  34. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  35. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  36. #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  37. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  38. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  39. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  40. #define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  41. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  42. (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
  43. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  44. #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  45. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  46. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  47. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  48. #ifdef CONFIG_FSL_ESDHC
  49. #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
  50. #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
  51. static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  52. {USDHC1_BASE_ADDR, 0, 8},
  53. {USDHC2_BASE_ADDR, 0, 4},
  54. {USDHC3_BASE_ADDR, 0, 4},
  55. };
  56. static iomux_cfg_t emmc0[] = {
  57. SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  58. SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  59. SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  60. SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  61. SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  62. SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  63. SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  64. SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  65. SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  66. SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  67. SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  68. SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  69. };
  70. static iomux_cfg_t usdhc2_sd[] = {
  71. SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  72. SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  73. SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  74. SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  75. SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  76. SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  77. SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  78. SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  79. SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  80. };
  81. int board_mmc_init(bd_t *bis)
  82. {
  83. int i, ret;
  84. /*
  85. * According to the board_mmc_init() the following map is done:
  86. * (U-Boot device node) (Physical Port)
  87. * mmc0 USDHC1
  88. * mmc1 USDHC2
  89. * mmc2 USDHC3
  90. */
  91. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  92. switch (i) {
  93. case 0:
  94. ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
  95. if (ret != SC_ERR_NONE)
  96. return ret;
  97. imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
  98. init_clk_usdhc(0);
  99. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  100. break;
  101. case 1:
  102. ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
  103. if (ret != SC_ERR_NONE)
  104. return ret;
  105. ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
  106. if (ret != SC_ERR_NONE)
  107. return ret;
  108. imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
  109. init_clk_usdhc(2);
  110. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  111. gpio_request(USDHC2_CD_GPIO, "sd2_cd");
  112. gpio_direction_input(USDHC2_CD_GPIO);
  113. break;
  114. default:
  115. printf("Warning: you configured more USDHC controllers"
  116. "(%d) than supported by the board\n", i + 1);
  117. return 0;
  118. }
  119. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  120. if (ret) {
  121. printf("Warning: failed to initialize mmc dev %d\n", i);
  122. return ret;
  123. }
  124. }
  125. return 0;
  126. }
  127. int board_mmc_getcd(struct mmc *mmc)
  128. {
  129. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  130. int ret = 0;
  131. switch (cfg->esdhc_base) {
  132. case USDHC1_BASE_ADDR:
  133. ret = 1;
  134. break;
  135. case USDHC2_BASE_ADDR:
  136. ret = !gpio_get_value(USDHC1_CD_GPIO);
  137. break;
  138. case USDHC3_BASE_ADDR:
  139. ret = !gpio_get_value(USDHC2_CD_GPIO);
  140. break;
  141. }
  142. return ret;
  143. }
  144. #endif /* CONFIG_FSL_ESDHC */
  145. void spl_board_init(void)
  146. {
  147. #if defined(CONFIG_SPL_SPI_SUPPORT)
  148. if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
  149. if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
  150. puts("Warning: failed to initialize FSPI0\n");
  151. }
  152. }
  153. #endif
  154. puts("Normal Boot\n");
  155. }
  156. void spl_board_prepare_for_boot(void)
  157. {
  158. #if defined(CONFIG_SPL_SPI_SUPPORT)
  159. if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
  160. if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
  161. puts("Warning: failed to turn off FSPI0\n");
  162. }
  163. }
  164. #endif
  165. }
  166. #ifdef CONFIG_SPL_LOAD_FIT
  167. int board_fit_config_name_match(const char *name)
  168. {
  169. /* Just empty function now - can't decide what to choose */
  170. debug("%s: %s\n", __func__, name);
  171. return 0;
  172. }
  173. #endif
  174. void board_init_f(ulong dummy)
  175. {
  176. /* Clear global data */
  177. memset((void *)gd, 0, sizeof(gd_t));
  178. arch_cpu_init();
  179. board_early_init_f();
  180. timer_init();
  181. preloader_console_init();
  182. /* Clear the BSS. */
  183. memset(__bss_start, 0, __bss_end - __bss_start);
  184. board_init_r(NULL, 0);
  185. }