ds414.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
  5. */
  6. #include <common.h>
  7. #include <miiphy.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/soc.h>
  11. #include <linux/mbus.h>
  12. #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  13. #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  14. #include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
  17. #define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
  18. #define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
  19. #define DS414_GPP_OUT_VAL_HIGH (0)
  20. #define DS414_GPP_OUT_POL_LOW (0)
  21. #define DS414_GPP_OUT_POL_MID (0)
  22. #define DS414_GPP_OUT_POL_HIGH (0)
  23. #define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
  24. #define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
  25. BIT(13) | BIT(14) | BIT(15)))
  26. #define DS414_GPP_OUT_ENA_HIGH (~0)
  27. static const u32 ds414_mpp_control[] = {
  28. 0x11111111,
  29. 0x22221111,
  30. 0x22222222,
  31. 0x00000000,
  32. 0x11110000,
  33. 0x00004000,
  34. 0x00000000,
  35. 0x00000000,
  36. 0x00000000
  37. };
  38. /* DDR3 static MC configuration */
  39. /* 1G_v1 (4x2Gbits) adapted by DS414 */
  40. MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
  41. {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
  42. {0x00001404, 0x30000800}, /*Dunit Control Low Register */
  43. {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
  44. {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
  45. {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
  46. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  47. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  48. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  49. {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
  50. {0x00001428, 0x000F8830}, /*Dunit Control High Register */
  51. {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
  52. {0x0000147C, 0x0000C671},
  53. {0x000014a0, 0x00000001},
  54. {0x000014a8, 0x00000100}, /*2:1 */
  55. {0x00020220, 0x00000006},
  56. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  57. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  58. {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
  59. {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
  60. {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
  61. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
  62. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  63. {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
  64. {0x000150C, 0x00000000}, /* CS1 Size */
  65. {0x0001514, 0x00000000}, /* CS2 Size */
  66. {0x000151C, 0x00000000}, /* CS3 Size */
  67. {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
  68. {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
  69. {0x000015D0, 0x00000650}, /*MR0 */
  70. {0x000015D4, 0x00000044}, /*MR1 */
  71. {0x000015D8, 0x00000010}, /*MR2 */
  72. {0x000015DC, 0x00000000}, /*MR3 */
  73. {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
  74. {0x000015EC, 0xF800A225}, /*DDR PHY */
  75. {0x0, 0x0}
  76. };
  77. MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  78. {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
  79. };
  80. extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
  81. MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
  82. { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
  83. { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
  84. PEX_BUS_DISABLED },
  85. 0x0040, serdes_change_m_phy
  86. }
  87. };
  88. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  89. {
  90. return &ds414_ddr_modes[0];
  91. }
  92. MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
  93. {
  94. return &ds414_serdes_cfg[0];
  95. }
  96. u8 board_sat_r_get(u8 dev_num, u8 reg)
  97. {
  98. return 0xf; /* All PEX ports support PCIe Gen2 */
  99. }
  100. int board_early_init_f(void)
  101. {
  102. int i;
  103. /* Set GPP Out value */
  104. reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
  105. reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
  106. reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
  107. /* set GPP polarity */
  108. reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
  109. reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
  110. reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
  111. /* Set GPP Out Enable */
  112. reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
  113. reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
  114. reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
  115. for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
  116. reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
  117. return 0;
  118. }
  119. int board_init(void)
  120. {
  121. u32 pwr_mng_ctrl_reg;
  122. /* Adress of boot parameters */
  123. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  124. /* Gate unused clocks
  125. *
  126. * Note: Disabling unused PCIe lanes will hang PCI bus scan.
  127. * Once this is resolved, bits 10-12, 26 and 27 can be
  128. * unset here as well.
  129. */
  130. pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
  131. pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
  132. pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
  133. pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
  134. pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
  135. pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
  136. pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
  137. pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
  138. reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
  139. return 0;
  140. }
  141. int checkboard(void)
  142. {
  143. puts("Board: DS414\n");
  144. return 0;
  145. }