board.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <i2c.h>
  8. #include <phy.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /* IO expander I2C device */
  14. #define I2C_IO_EXP_ADDR 0x22
  15. #define I2C_IO_CFG_REG_0 0x6
  16. #define I2C_IO_DATA_OUT_REG_0 0x2
  17. #define I2C_IO_REG_0_SATA_OFF 2
  18. #define I2C_IO_REG_0_USB_H_OFF 1
  19. /* The pin control values are the same for DB and Espressobin */
  20. #define PINCTRL_NB_REG_VALUE 0x000173fa
  21. #define PINCTRL_SB_REG_VALUE 0x00007a23
  22. /* Ethernet switch registers */
  23. /* SMI addresses for multi-chip mode */
  24. #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
  25. #define MVEBU_SW_G2_SMI_ADDR (28)
  26. /* Multi-chip mode */
  27. #define MVEBU_SW_SMI_DATA_REG (1)
  28. #define MVEBU_SW_SMI_CMD_REG (0)
  29. #define SW_SMI_CMD_REG_ADDR_OFF 0
  30. #define SW_SMI_CMD_DEV_ADDR_OFF 5
  31. #define SW_SMI_CMD_SMI_OP_OFF 10
  32. #define SW_SMI_CMD_SMI_MODE_OFF 12
  33. #define SW_SMI_CMD_SMI_BUSY_OFF 15
  34. /* Single-chip mode */
  35. /* Switch Port Registers */
  36. #define MVEBU_SW_LINK_CTRL_REG (1)
  37. #define MVEBU_SW_PORT_CTRL_REG (4)
  38. /* Global 2 Registers */
  39. #define MVEBU_G2_SMI_PHY_CMD_REG (24)
  40. #define MVEBU_G2_SMI_PHY_DATA_REG (25)
  41. int board_early_init_f(void)
  42. {
  43. return 0;
  44. }
  45. int board_init(void)
  46. {
  47. /* adress of boot parameters */
  48. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  49. return 0;
  50. }
  51. /* Board specific AHCI / SATA enable code */
  52. int board_ahci_enable(void)
  53. {
  54. struct udevice *dev;
  55. int ret;
  56. u8 buf[8];
  57. /* Only DB requres this configuration */
  58. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  59. return 0;
  60. /* Configure IO exander PCA9555: 7bit address 0x22 */
  61. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  62. if (ret) {
  63. printf("Cannot find PCA9555: %d\n", ret);
  64. return 0;
  65. }
  66. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  67. if (ret) {
  68. printf("Failed to read IO expander value via I2C\n");
  69. return -EIO;
  70. }
  71. /*
  72. * Enable SATA power via IO expander connected via I2C by setting
  73. * the corresponding bit to output mode to enable power for SATA
  74. */
  75. buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
  76. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  77. if (ret) {
  78. printf("Failed to set IO expander via I2C\n");
  79. return -EIO;
  80. }
  81. return 0;
  82. }
  83. /* Board specific xHCI enable code */
  84. int board_xhci_enable(fdt_addr_t base)
  85. {
  86. struct udevice *dev;
  87. int ret;
  88. u8 buf[8];
  89. /* Only DB requres this configuration */
  90. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  91. return 0;
  92. /* Configure IO exander PCA9555: 7bit address 0x22 */
  93. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  94. if (ret) {
  95. printf("Cannot find PCA9555: %d\n", ret);
  96. return 0;
  97. }
  98. printf("Enable USB VBUS\n");
  99. /*
  100. * Read configuration (direction) and set VBUS pin as output
  101. * (reset pin = output)
  102. */
  103. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  104. if (ret) {
  105. printf("Failed to read IO expander value via I2C\n");
  106. return -EIO;
  107. }
  108. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  109. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  110. if (ret) {
  111. printf("Failed to set IO expander via I2C\n");
  112. return -EIO;
  113. }
  114. /* Read VBUS output value and disable it */
  115. ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  116. if (ret) {
  117. printf("Failed to read IO expander value via I2C\n");
  118. return -EIO;
  119. }
  120. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  121. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  122. if (ret) {
  123. printf("Failed to set IO expander via I2C\n");
  124. return -EIO;
  125. }
  126. /*
  127. * Required delay for configuration to settle - must wait for
  128. * power on port is disabled in case VBUS signal was high,
  129. * required 3 seconds delay to let VBUS signal fully settle down
  130. */
  131. mdelay(3000);
  132. /* Enable VBUS power: Set output value of VBUS pin as enabled */
  133. buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
  134. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  135. if (ret) {
  136. printf("Failed to set IO expander via I2C\n");
  137. return -EIO;
  138. }
  139. mdelay(500); /* required delay to let output value settle */
  140. return 0;
  141. }
  142. /* Helper function for accessing switch devices in multi-chip connection mode */
  143. static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
  144. int smi_addr, int reg, u16 value)
  145. {
  146. u16 smi_cmd = 0;
  147. if (bus->write(bus, dev_smi_addr, 0,
  148. MVEBU_SW_SMI_DATA_REG, value) != 0) {
  149. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  150. smi_addr, reg);
  151. return -EFAULT;
  152. }
  153. smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
  154. (1 << SW_SMI_CMD_SMI_MODE_OFF) |
  155. (1 << SW_SMI_CMD_SMI_OP_OFF) |
  156. (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
  157. (reg << SW_SMI_CMD_REG_ADDR_OFF);
  158. if (bus->write(bus, dev_smi_addr, 0,
  159. MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
  160. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  161. smi_addr, reg);
  162. return -EFAULT;
  163. }
  164. return 0;
  165. }
  166. /* Bring-up board-specific network stuff */
  167. int board_network_enable(struct mii_dev *bus)
  168. {
  169. if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
  170. return 0;
  171. /*
  172. * FIXME: remove this code once Topaz driver gets available
  173. * A3720 Community Board Only
  174. * Configure Topaz switch (88E6341)
  175. * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
  176. */
  177. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  178. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  179. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  180. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  181. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  182. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  183. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  184. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  185. /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
  186. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  187. MVEBU_SW_LINK_CTRL_REG, 0xe002);
  188. /* Power up PHY 1, 2, 3 (through Global 2 registers) */
  189. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  190. MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
  191. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  192. MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
  193. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  194. MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
  195. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  196. MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
  197. return 0;
  198. }