dreamplug.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * Jason Cooper <u-boot@lakedaemon.net>
  5. *
  6. * Based on work by:
  7. * Marvell Semiconductor <www.marvell.com>
  8. * Written-by: Siddarth Gore <gores@marvell.com>
  9. */
  10. #include <common.h>
  11. #include <miiphy.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <asm/arch/mpp.h>
  15. #include "dreamplug.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. int board_early_init_f(void)
  18. {
  19. /*
  20. * default gpio configuration
  21. * There are maximum 64 gpios controlled through 2 sets of registers
  22. * the below configuration configures mainly initial LED status
  23. */
  24. mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
  25. DREAMPLUG_OE_VAL_HIGH,
  26. DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
  27. /* Multi-Purpose Pins Functionality configuration */
  28. static const u32 kwmpp_config[] = {
  29. MPP0_SPI_SCn, /* SPI Flash */
  30. MPP1_SPI_MOSI,
  31. MPP2_SPI_SCK,
  32. MPP3_SPI_MISO,
  33. MPP4_NF_IO6,
  34. MPP5_NF_IO7,
  35. MPP6_SYSRST_OUTn,
  36. MPP7_GPO,
  37. MPP8_TW_SDA,
  38. MPP9_TW_SCK,
  39. MPP10_UART0_TXD, /* Serial */
  40. MPP11_UART0_RXD,
  41. MPP12_SD_CLK, /* SDIO Slot */
  42. MPP13_SD_CMD,
  43. MPP14_SD_D0,
  44. MPP15_SD_D1,
  45. MPP16_SD_D2,
  46. MPP17_SD_D3,
  47. MPP18_NF_IO0,
  48. MPP19_NF_IO1,
  49. MPP20_GE1_0, /* Gigabit Ethernet */
  50. MPP21_GE1_1,
  51. MPP22_GE1_2,
  52. MPP23_GE1_3,
  53. MPP24_GE1_4,
  54. MPP25_GE1_5,
  55. MPP26_GE1_6,
  56. MPP27_GE1_7,
  57. MPP28_GE1_8,
  58. MPP29_GE1_9,
  59. MPP30_GE1_10,
  60. MPP31_GE1_11,
  61. MPP32_GE1_12,
  62. MPP33_GE1_13,
  63. MPP34_GE1_14,
  64. MPP35_GE1_15,
  65. MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
  66. MPP37_GPIO,
  67. MPP38_GPIO,
  68. MPP39_GPIO,
  69. MPP40_TDM_SPI_SCK,
  70. MPP41_TDM_SPI_MISO,
  71. MPP42_TDM_SPI_MOSI,
  72. MPP43_GPIO,
  73. MPP44_GPIO,
  74. MPP45_GPIO,
  75. MPP46_GPIO,
  76. MPP47_GPIO, /* Bluetooth LED */
  77. MPP48_GPIO, /* Wifi LED */
  78. MPP49_GPIO, /* Wifi AP LED */
  79. 0
  80. };
  81. kirkwood_mpp_conf(kwmpp_config, NULL);
  82. return 0;
  83. }
  84. int board_init(void)
  85. {
  86. /* adress of boot parameters */
  87. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  88. return 0;
  89. }
  90. #ifdef CONFIG_RESET_PHY_R
  91. void mv_phy_88e1116_init(char *name)
  92. {
  93. u16 reg;
  94. u16 devadr;
  95. if (miiphy_set_current_dev(name))
  96. return;
  97. /* command to read PHY dev address */
  98. if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  99. printf("Err..%s could not read PHY dev address\n",
  100. __func__);
  101. return;
  102. }
  103. /*
  104. * Enable RGMII delay on Tx and Rx for CPU port
  105. * Ref: sec 4.7.2 of chip datasheet
  106. */
  107. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  108. miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
  109. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  110. miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
  111. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  112. /* reset the phy */
  113. miiphy_reset(name, devadr);
  114. printf("88E1116 Initialized on %s\n", name);
  115. }
  116. void reset_phy(void)
  117. {
  118. /* configure and initialize both PHY's */
  119. mv_phy_88e1116_init("egiga0");
  120. mv_phy_88e1116_init("egiga1");
  121. }
  122. #endif /* CONFIG_RESET_PHY_R */