db-mv784mp-gp.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <miiphy.h>
  7. #include <netdev.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/soc.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #define ETH_PHY_CTRL_REG 0
  13. #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
  14. #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
  15. /*
  16. * Those values and defines are taken from the Marvell U-Boot version
  17. * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
  18. * "RD-AXP-GP rev 1.0".
  19. *
  20. * GPPs
  21. * MPP# NAME IN/OUT
  22. * ----------------------------------------------
  23. * 21 SW_Reset_ OUT
  24. * 25 Phy_Int# IN
  25. * 28 SDI_WP IN
  26. * 29 SDI_Status IN
  27. * 54-61 On GPP Connector ?
  28. * 62 Switch Interrupt IN
  29. * 63-65 Reserved from SW Board ?
  30. * 66 SW_BRD connected IN
  31. */
  32. #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
  33. #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
  34. #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
  35. #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
  36. #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
  37. #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
  38. int board_early_init_f(void)
  39. {
  40. /* Configure MPP */
  41. writel(0x00000000, MVEBU_MPP_BASE + 0x00);
  42. writel(0x00000000, MVEBU_MPP_BASE + 0x04);
  43. writel(0x33000000, MVEBU_MPP_BASE + 0x08);
  44. writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
  45. writel(0x11111111, MVEBU_MPP_BASE + 0x10);
  46. writel(0x00221100, MVEBU_MPP_BASE + 0x14);
  47. writel(0x00000003, MVEBU_MPP_BASE + 0x18);
  48. writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
  49. writel(0x00000000, MVEBU_MPP_BASE + 0x20);
  50. /* Configure GPIO */
  51. writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  52. writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  53. writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  54. writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  55. writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
  56. writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
  57. return 0;
  58. }
  59. int board_init(void)
  60. {
  61. /* adress of boot parameters */
  62. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  63. return 0;
  64. }
  65. int checkboard(void)
  66. {
  67. puts("Board: Marvell DB-MV784MP-GP\n");
  68. return 0;
  69. }
  70. int board_eth_init(bd_t *bis)
  71. {
  72. cpu_eth_init(bis); /* Built in controller(s) come first */
  73. return pci_eth_init(bis);
  74. }
  75. int board_phy_config(struct phy_device *phydev)
  76. {
  77. u16 reg;
  78. /* Enable QSGMII AN */
  79. /* Set page to 4 */
  80. phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
  81. /* Enable AN */
  82. phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
  83. /* Set page to 0 */
  84. phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
  85. /* Phy C_ANEG */
  86. reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
  87. reg |= 0x1E0;
  88. phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
  89. /* Soft-Reset */
  90. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
  91. phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
  92. /* Power up the phy */
  93. reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
  94. reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
  95. phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
  96. printf("88E1545 Initialized\n");
  97. return 0;
  98. }