db-88f6820-gp.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <miiphy.h>
  8. #include <netdev.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  13. #include <../serdes/a38x/high_speed_env_spec.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /*
  16. * Those values and defines are taken from the Marvell U-Boot version
  17. * "u-boot-2013.01-2014_T3.0"
  18. */
  19. #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
  20. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  21. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  22. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  23. #define DB_GP_88F68XX_GPP_OUT_ENA_MID \
  24. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  25. BIT(16) | BIT(17) | BIT(18)))
  26. #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
  27. #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
  28. #define DB_GP_88F68XX_GPP_POL_LOW 0x0
  29. #define DB_GP_88F68XX_GPP_POL_MID 0x0
  30. /* IO expander on Marvell GP board includes e.g. fan enabling */
  31. struct marvell_io_exp {
  32. u8 chip;
  33. u8 addr;
  34. u8 val;
  35. };
  36. static struct marvell_io_exp io_exp[] = {
  37. { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  38. { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  39. { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  40. { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  41. { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  42. { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
  43. { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  44. { 0x21, 3, 0xC0 } /* Output Data, register#1 */
  45. };
  46. static struct serdes_map board_serdes_map[] = {
  47. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  48. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  49. {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  50. {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  51. {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  52. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  53. };
  54. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  55. {
  56. *serdes_map_array = board_serdes_map;
  57. *count = ARRAY_SIZE(board_serdes_map);
  58. return 0;
  59. }
  60. /*
  61. * Define the DDR layout / topology here in the board file. This will
  62. * be used by the DDR3 init code in the SPL U-Boot version to configure
  63. * the DDR3 controller.
  64. */
  65. static struct mv_ddr_topology_map board_topology_map = {
  66. DEBUG_LEVEL_ERROR,
  67. 0x1, /* active interfaces */
  68. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  69. { { { {0x1, 0, 0, 0},
  70. {0x1, 0, 0, 0},
  71. {0x1, 0, 0, 0},
  72. {0x1, 0, 0, 0},
  73. {0x1, 0, 0, 0} },
  74. SPEED_BIN_DDR_1866L, /* speed_bin */
  75. MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
  76. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  77. MV_DDR_FREQ_800, /* frequency */
  78. 0, 0, /* cas_wl cas_l */
  79. MV_DDR_TEMP_LOW, /* temperature */
  80. MV_DDR_TIM_DEFAULT} }, /* timing */
  81. BUS_MASK_32BIT, /* Busses mask */
  82. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  83. { {0} }, /* raw spd data */
  84. {0} /* timing parameters */
  85. };
  86. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  87. {
  88. /* Return the board topology as defined in the board code */
  89. return &board_topology_map;
  90. }
  91. int board_early_init_f(void)
  92. {
  93. /* Configure MPP */
  94. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  95. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  96. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  97. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  98. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  99. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  100. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  101. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  102. /* Set GPP Out value */
  103. writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  104. writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  105. /* Set GPP Polarity */
  106. writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  107. writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  108. /* Set GPP Out Enable */
  109. writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  110. writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  111. return 0;
  112. }
  113. int board_init(void)
  114. {
  115. int i;
  116. /* adress of boot parameters */
  117. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  118. /* Init I2C IO expanders */
  119. for (i = 0; i < ARRAY_SIZE(io_exp); i++)
  120. i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
  121. return 0;
  122. }
  123. int checkboard(void)
  124. {
  125. puts("Board: Marvell DB-88F6820-GP\n");
  126. return 0;
  127. }
  128. int board_eth_init(bd_t *bis)
  129. {
  130. cpu_eth_init(bis); /* Built in controller(s) come first */
  131. return pci_eth_init(bis);
  132. }