flea3.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  4. *
  5. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  6. *
  7. * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <env.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/iomux-mx35.h>
  16. #include <i2c.h>
  17. #include <linux/types.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <netdev.h>
  21. #include <fdt_support.h>
  22. #include <mtd_node.h>
  23. #include <jffs2/load_kernel.h>
  24. #ifndef CONFIG_BOARD_EARLY_INIT_F
  25. #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  26. #endif
  27. #define CCM_CCMR_CONFIG 0x003F4208
  28. #define ESDCTL_DDR2_CONFIG 0x007FFC3F
  29. static inline void dram_wait(unsigned int count)
  30. {
  31. volatile unsigned int wait = count;
  32. while (wait--)
  33. ;
  34. }
  35. DECLARE_GLOBAL_DATA_PTR;
  36. int dram_init(void)
  37. {
  38. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  39. PHYS_SDRAM_1_SIZE);
  40. return 0;
  41. }
  42. static void board_setup_sdram(void)
  43. {
  44. struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  45. /* Initialize with default values both CSD0/1 */
  46. writel(0x2000, &esdc->esdctl0);
  47. writel(0x2000, &esdc->esdctl1);
  48. mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
  49. 13, 10, 2, 0x8080);
  50. }
  51. static void setup_iomux_uart3(void)
  52. {
  53. static const iomux_v3_cfg_t uart3_pads[] = {
  54. MX35_PAD_RTS2__UART3_RXD_MUX,
  55. MX35_PAD_CTS2__UART3_TXD_MUX,
  56. };
  57. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  58. }
  59. #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  60. static void setup_iomux_i2c(void)
  61. {
  62. static const iomux_v3_cfg_t i2c_pads[] = {
  63. NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  64. NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  65. NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
  66. NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
  67. };
  68. imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  69. }
  70. static void setup_iomux_spi(void)
  71. {
  72. static const iomux_v3_cfg_t spi_pads[] = {
  73. MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  74. MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  75. MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  76. MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  77. MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  78. };
  79. imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  80. }
  81. static void setup_iomux_fec(void)
  82. {
  83. static const iomux_v3_cfg_t fec_pads[] = {
  84. MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
  85. MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
  86. MX35_PAD_FEC_RX_DV__FEC_RX_DV,
  87. MX35_PAD_FEC_COL__FEC_COL,
  88. MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
  89. MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
  90. MX35_PAD_FEC_TX_EN__FEC_TX_EN,
  91. MX35_PAD_FEC_MDC__FEC_MDC,
  92. MX35_PAD_FEC_MDIO__FEC_MDIO,
  93. MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
  94. MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
  95. MX35_PAD_FEC_CRS__FEC_CRS,
  96. MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
  97. MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
  98. MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
  99. MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
  100. MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
  101. MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
  102. /* GPIO used to power off ethernet */
  103. MX35_PAD_STXFS4__GPIO2_31,
  104. };
  105. /* setup pins for FEC */
  106. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  107. }
  108. int board_early_init_f(void)
  109. {
  110. struct ccm_regs *ccm =
  111. (struct ccm_regs *)IMX_CCM_BASE;
  112. /* setup GPIO3_1 to set HighVCore signal */
  113. imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
  114. gpio_direction_output(65, 1);
  115. /* initialize PLL and clock configuration */
  116. writel(CCM_CCMR_CONFIG, &ccm->ccmr);
  117. writel(CCM_MPLL_532_HZ, &ccm->mpctl);
  118. writel(CCM_PPLL_300_HZ, &ccm->ppctl);
  119. /* Set the core to run at 532 Mhz */
  120. writel(0x00001000, &ccm->pdr0);
  121. /* Set-up RAM */
  122. board_setup_sdram();
  123. /* enable clocks */
  124. writel(readl(&ccm->cgr0) |
  125. MXC_CCM_CGR0_EMI_MASK |
  126. MXC_CCM_CGR0_EDIO_MASK |
  127. MXC_CCM_CGR0_EPIT1_MASK,
  128. &ccm->cgr0);
  129. writel(readl(&ccm->cgr1) |
  130. MXC_CCM_CGR1_FEC_MASK |
  131. MXC_CCM_CGR1_GPIO1_MASK |
  132. MXC_CCM_CGR1_GPIO2_MASK |
  133. MXC_CCM_CGR1_GPIO3_MASK |
  134. MXC_CCM_CGR1_I2C1_MASK |
  135. MXC_CCM_CGR1_I2C2_MASK |
  136. MXC_CCM_CGR1_I2C3_MASK,
  137. &ccm->cgr1);
  138. /* Set-up NAND */
  139. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  140. /* Set pinmux for the required peripherals */
  141. setup_iomux_uart3();
  142. setup_iomux_i2c();
  143. setup_iomux_fec();
  144. setup_iomux_spi();
  145. return 0;
  146. }
  147. int board_init(void)
  148. {
  149. /* address of boot parameters */
  150. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  151. /* Enable power for ethernet */
  152. gpio_direction_output(63, 0);
  153. udelay(2000);
  154. return 0;
  155. }
  156. u32 get_board_rev(void)
  157. {
  158. int rev = 0;
  159. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  160. }
  161. /*
  162. * called prior to booting kernel or by 'fdt boardsetup' command
  163. *
  164. */
  165. int ft_board_setup(void *blob, bd_t *bd)
  166. {
  167. static const struct node_info nodes[] = {
  168. { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
  169. { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  170. };
  171. if (env_get("fdt_noauto")) {
  172. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  173. return 0;
  174. }
  175. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  176. return 0;
  177. }