misc.S 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Miscellaneous assembly functions.
  4. *
  5. * Copyright (C) 2001 - 2007 Tensilica Inc.
  6. * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
  7. *
  8. * Chris Zankel <chris@zankel.net>
  9. */
  10. #include <linux/linkage.h>
  11. #include <asm/asmmacro.h>
  12. #include <asm/cacheasm.h>
  13. /*
  14. * void __invalidate_icache_page(ulong start)
  15. */
  16. ENTRY(__invalidate_icache_page)
  17. abi_entry
  18. ___invalidate_icache_page a2 a3
  19. isync
  20. abi_ret
  21. ENDPROC(__invalidate_icache_page)
  22. /*
  23. * void __invalidate_dcache_page(ulong start)
  24. */
  25. ENTRY(__invalidate_dcache_page)
  26. abi_entry
  27. ___invalidate_dcache_page a2 a3
  28. dsync
  29. abi_ret
  30. ENDPROC(__invalidate_dcache_page)
  31. /*
  32. * void __flush_invalidate_dcache_page(ulong start)
  33. */
  34. ENTRY(__flush_invalidate_dcache_page)
  35. abi_entry
  36. ___flush_invalidate_dcache_page a2 a3
  37. dsync
  38. abi_ret
  39. ENDPROC(__flush_invalidate_dcache_page)
  40. /*
  41. * void __flush_dcache_page(ulong start)
  42. */
  43. ENTRY(__flush_dcache_page)
  44. abi_entry
  45. ___flush_dcache_page a2 a3
  46. dsync
  47. abi_ret
  48. ENDPROC(__flush_dcache_page)
  49. /*
  50. * void __invalidate_icache_range(ulong start, ulong size)
  51. */
  52. ENTRY(__invalidate_icache_range)
  53. abi_entry
  54. ___invalidate_icache_range a2 a3 a4
  55. isync
  56. abi_ret
  57. ENDPROC(__invalidate_icache_range)
  58. /*
  59. * void __flush_invalidate_dcache_range(ulong start, ulong size)
  60. */
  61. ENTRY(__flush_invalidate_dcache_range)
  62. abi_entry
  63. ___flush_invalidate_dcache_range a2 a3 a4
  64. dsync
  65. abi_ret
  66. ENDPROC(__flush_invalidate_dcache_range)
  67. /*
  68. * void _flush_dcache_range(ulong start, ulong size)
  69. */
  70. ENTRY(__flush_dcache_range)
  71. abi_entry
  72. ___flush_dcache_range a2 a3 a4
  73. dsync
  74. abi_ret
  75. ENDPROC(__flush_dcache_range)
  76. /*
  77. * void _invalidate_dcache_range(ulong start, ulong size)
  78. */
  79. ENTRY(__invalidate_dcache_range)
  80. abi_entry
  81. ___invalidate_dcache_range a2 a3 a4
  82. abi_ret
  83. ENDPROC(__invalidate_dcache_range)
  84. /*
  85. * void _invalidate_icache_all(void)
  86. */
  87. ENTRY(__invalidate_icache_all)
  88. abi_entry
  89. ___invalidate_icache_all a2 a3
  90. isync
  91. abi_ret
  92. ENDPROC(__invalidate_icache_all)
  93. /*
  94. * void _flush_invalidate_dcache_all(void)
  95. */
  96. ENTRY(__flush_invalidate_dcache_all)
  97. abi_entry
  98. ___flush_invalidate_dcache_all a2 a3
  99. dsync
  100. abi_ret
  101. ENDPROC(__flush_invalidate_dcache_all)
  102. /*
  103. * void _invalidate_dcache_all(void)
  104. */
  105. ENTRY(__invalidate_dcache_all)
  106. abi_entry
  107. ___invalidate_dcache_all a2 a3
  108. dsync
  109. abi_ret
  110. ENDPROC(__invalidate_dcache_all)