xtfpga.dtsi 2.8 KB

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  1. / {
  2. compatible = "cdns,xtensa-xtfpga";
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. interrupt-parent = <&pic>;
  6. chosen {
  7. bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
  8. };
  9. memory@0 {
  10. device_type = "memory";
  11. reg = <0x00000000 0x06000000>;
  12. };
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. compatible = "cdns,xtensa-cpu";
  18. reg = <0>;
  19. /* Filled in by platform_setup from FPGA register
  20. * clock-frequency = <100000000>;
  21. */
  22. };
  23. };
  24. pic: pic {
  25. compatible = "cdns,xtensa-pic";
  26. /* one cell: internal irq number,
  27. * two cells: second cell == 0: internal irq number
  28. * second cell == 1: external irq number
  29. */
  30. #interrupt-cells = <2>;
  31. interrupt-controller;
  32. };
  33. clocks {
  34. osc: main-oscillator {
  35. #clock-cells = <0>;
  36. compatible = "fixed-clock";
  37. };
  38. clk54: clk54 {
  39. #clock-cells = <0>;
  40. compatible = "fixed-clock";
  41. clock-frequency = <54000000>;
  42. };
  43. };
  44. soc {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. compatible = "simple-bus";
  48. ranges = <0x00000000 0xf0000000 0x10000000>;
  49. serial0: serial@0d050020 {
  50. device_type = "serial";
  51. compatible = "ns16550a";
  52. no-loopback-test;
  53. reg = <0x0d050020 0x20>;
  54. reg-shift = <2>;
  55. reg-io-width = <4>;
  56. native-endian;
  57. interrupts = <0 1>; /* external irq 0 */
  58. clocks = <&osc>;
  59. };
  60. enet0: ethoc@0d030000 {
  61. compatible = "opencores,ethoc";
  62. reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
  63. native-endian;
  64. interrupts = <1 1>; /* external irq 1 */
  65. local-mac-address = [00 50 c2 13 6f 00];
  66. clocks = <&osc>;
  67. };
  68. i2s0: xtfpga-i2s@0d080000 {
  69. #sound-dai-cells = <0>;
  70. compatible = "cdns,xtfpga-i2s";
  71. reg = <0x0d080000 0x40>;
  72. interrupts = <2 1>; /* external irq 2 */
  73. clocks = <&cdce706 4>;
  74. };
  75. i2c0: i2c-master@0d090000 {
  76. compatible = "opencores,i2c-ocores";
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. reg = <0x0d090000 0x20>;
  80. reg-shift = <2>;
  81. reg-io-width = <4>;
  82. native-endian;
  83. interrupts = <4 1>;
  84. clocks = <&osc>;
  85. cdce706: clock-synth@69 {
  86. compatible = "ti,cdce706";
  87. #clock-cells = <1>;
  88. reg = <0x69>;
  89. clocks = <&clk54>;
  90. clock-names = "clk_in0";
  91. };
  92. };
  93. spi0: spi-master@0d0a0000 {
  94. compatible = "cdns,xtfpga-spi";
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. reg = <0x0d0a0000 0xc>;
  98. tlv320aic23: sound-codec@0 {
  99. #sound-dai-cells = <0>;
  100. compatible = "tlv320aic23";
  101. reg = <0>;
  102. spi-max-frequency = <12500000>;
  103. };
  104. };
  105. };
  106. sound {
  107. compatible = "simple-audio-card";
  108. simple-audio-card,format = "i2s";
  109. simple-audio-card,mclk-fs = <256>;
  110. simple-audio-card,cpu {
  111. sound-dai = <&i2s0>;
  112. };
  113. simple-audio-card,codec {
  114. sound-dai = <&tlv320aic23>;
  115. simple-audio-card,bitclock-master = <0>;
  116. simple-audio-card,frame-master = <0>;
  117. clocks = <&cdce706 4>;
  118. };
  119. };
  120. };