mpspec.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Adapted from coreboot src/arch/x86/boot/mpspec.c
  6. */
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <asm/cpu.h>
  13. #include <asm/irq.h>
  14. #include <asm/ioapic.h>
  15. #include <asm/lapic.h>
  16. #include <asm/mpspec.h>
  17. #include <asm/tables.h>
  18. #include <dm/uclass-internal.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static bool isa_irq_occupied[16];
  21. struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
  22. {
  23. ulong mc;
  24. memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
  25. mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
  26. mf->mpf_length = 1;
  27. mf->mpf_spec = MPSPEC_V14;
  28. mf->mpf_checksum = 0;
  29. /* We don't use the default configuration table */
  30. mf->mpf_feature1 = 0;
  31. /* Indicate that virtual wire mode is always implemented */
  32. mf->mpf_feature2 = 0;
  33. mf->mpf_feature3 = 0;
  34. mf->mpf_feature4 = 0;
  35. mf->mpf_feature5 = 0;
  36. mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
  37. mc = (ulong)mf + sizeof(struct mp_floating_table);
  38. return (struct mp_config_table *)mc;
  39. }
  40. void mp_config_table_init(struct mp_config_table *mc)
  41. {
  42. memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
  43. mc->mpc_length = sizeof(struct mp_config_table);
  44. mc->mpc_spec = MPSPEC_V14;
  45. mc->mpc_checksum = 0;
  46. mc->mpc_oemptr = 0;
  47. mc->mpc_oemsize = 0;
  48. mc->mpc_entry_count = 0;
  49. mc->mpc_lapic = LAPIC_DEFAULT_BASE;
  50. mc->mpe_length = 0;
  51. mc->mpe_checksum = 0;
  52. mc->reserved = 0;
  53. /* The oem/product id fields are exactly 8/12 bytes long */
  54. table_fill_string(mc->mpc_oem, CONFIG_SYS_VENDOR, 8, ' ');
  55. table_fill_string(mc->mpc_product, CONFIG_SYS_BOARD, 12, ' ');
  56. }
  57. void mp_write_processor(struct mp_config_table *mc)
  58. {
  59. struct mpc_config_processor *mpc;
  60. struct udevice *dev;
  61. u8 boot_apicid, apicver;
  62. u32 cpusignature, cpufeature;
  63. struct cpuid_result result;
  64. boot_apicid = lapicid();
  65. apicver = lapic_read(LAPIC_LVR) & 0xff;
  66. result = cpuid(1);
  67. cpusignature = result.eax;
  68. cpufeature = result.edx;
  69. for (uclass_find_first_device(UCLASS_CPU, &dev);
  70. dev;
  71. uclass_find_next_device(&dev)) {
  72. struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  73. u8 cpuflag = MPC_CPU_EN;
  74. if (!device_active(dev))
  75. continue;
  76. mpc = (struct mpc_config_processor *)mp_next_mpc_entry(mc);
  77. mpc->mpc_type = MP_PROCESSOR;
  78. mpc->mpc_apicid = plat->cpu_id;
  79. mpc->mpc_apicver = apicver;
  80. if (boot_apicid == plat->cpu_id)
  81. cpuflag |= MPC_CPU_BP;
  82. mpc->mpc_cpuflag = cpuflag;
  83. mpc->mpc_cpusignature = cpusignature;
  84. mpc->mpc_cpufeature = cpufeature;
  85. mpc->mpc_reserved[0] = 0;
  86. mpc->mpc_reserved[1] = 0;
  87. mp_add_mpc_entry(mc, sizeof(*mpc));
  88. }
  89. }
  90. void mp_write_bus(struct mp_config_table *mc, int id, const char *bustype)
  91. {
  92. struct mpc_config_bus *mpc;
  93. mpc = (struct mpc_config_bus *)mp_next_mpc_entry(mc);
  94. mpc->mpc_type = MP_BUS;
  95. mpc->mpc_busid = id;
  96. memcpy(mpc->mpc_bustype, bustype, 6);
  97. mp_add_mpc_entry(mc, sizeof(*mpc));
  98. }
  99. void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr)
  100. {
  101. struct mpc_config_ioapic *mpc;
  102. mpc = (struct mpc_config_ioapic *)mp_next_mpc_entry(mc);
  103. mpc->mpc_type = MP_IOAPIC;
  104. mpc->mpc_apicid = id;
  105. mpc->mpc_apicver = ver;
  106. mpc->mpc_flags = MPC_APIC_USABLE;
  107. mpc->mpc_apicaddr = apicaddr;
  108. mp_add_mpc_entry(mc, sizeof(*mpc));
  109. }
  110. void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
  111. int srcbus, int srcbusirq, int dstapic, int dstirq)
  112. {
  113. struct mpc_config_intsrc *mpc;
  114. mpc = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
  115. mpc->mpc_type = MP_INTSRC;
  116. mpc->mpc_irqtype = irqtype;
  117. mpc->mpc_irqflag = irqflag;
  118. mpc->mpc_srcbus = srcbus;
  119. mpc->mpc_srcbusirq = srcbusirq;
  120. mpc->mpc_dstapic = dstapic;
  121. mpc->mpc_dstirq = dstirq;
  122. mp_add_mpc_entry(mc, sizeof(*mpc));
  123. }
  124. void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
  125. int srcbus, int dev, int pin, int dstapic, int dstirq)
  126. {
  127. u8 srcbusirq = (dev << 2) | (pin - 1);
  128. mp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
  129. srcbus, srcbusirq, dstapic, dstirq);
  130. }
  131. void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
  132. int srcbus, int srcbusirq, int destapic, int destlint)
  133. {
  134. struct mpc_config_lintsrc *mpc;
  135. mpc = (struct mpc_config_lintsrc *)mp_next_mpc_entry(mc);
  136. mpc->mpc_type = MP_LINTSRC;
  137. mpc->mpc_irqtype = irqtype;
  138. mpc->mpc_irqflag = irqflag;
  139. mpc->mpc_srcbusid = srcbus;
  140. mpc->mpc_srcbusirq = srcbusirq;
  141. mpc->mpc_destapic = destapic;
  142. mpc->mpc_destlint = destlint;
  143. mp_add_mpc_entry(mc, sizeof(*mpc));
  144. }
  145. void mp_write_address_space(struct mp_config_table *mc,
  146. int busid, int addr_type,
  147. u32 addr_base_low, u32 addr_base_high,
  148. u32 addr_length_low, u32 addr_length_high)
  149. {
  150. struct mp_ext_system_address_space *mpe;
  151. mpe = (struct mp_ext_system_address_space *)mp_next_mpe_entry(mc);
  152. mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
  153. mpe->mpe_length = sizeof(*mpe);
  154. mpe->mpe_busid = busid;
  155. mpe->mpe_addr_type = addr_type;
  156. mpe->mpe_addr_base_low = addr_base_low;
  157. mpe->mpe_addr_base_high = addr_base_high;
  158. mpe->mpe_addr_length_low = addr_length_low;
  159. mpe->mpe_addr_length_high = addr_length_high;
  160. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  161. }
  162. void mp_write_bus_hierarchy(struct mp_config_table *mc,
  163. int busid, int bus_info, int parent_busid)
  164. {
  165. struct mp_ext_bus_hierarchy *mpe;
  166. mpe = (struct mp_ext_bus_hierarchy *)mp_next_mpe_entry(mc);
  167. mpe->mpe_type = MPE_BUS_HIERARCHY;
  168. mpe->mpe_length = sizeof(*mpe);
  169. mpe->mpe_busid = busid;
  170. mpe->mpe_bus_info = bus_info;
  171. mpe->mpe_parent_busid = parent_busid;
  172. mpe->reserved[0] = 0;
  173. mpe->reserved[1] = 0;
  174. mpe->reserved[2] = 0;
  175. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  176. }
  177. void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
  178. int addr_modifier, u32 range_list)
  179. {
  180. struct mp_ext_compat_address_space *mpe;
  181. mpe = (struct mp_ext_compat_address_space *)mp_next_mpe_entry(mc);
  182. mpe->mpe_type = MPE_COMPAT_ADDRESS_SPACE;
  183. mpe->mpe_length = sizeof(*mpe);
  184. mpe->mpe_busid = busid;
  185. mpe->mpe_addr_modifier = addr_modifier;
  186. mpe->mpe_range_list = range_list;
  187. mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
  188. }
  189. u32 mptable_finalize(struct mp_config_table *mc)
  190. {
  191. ulong end;
  192. mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
  193. mc->mpe_length);
  194. mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
  195. end = mp_next_mpe_entry(mc);
  196. debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
  197. return end;
  198. }
  199. static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
  200. int apicid, int external_int2)
  201. {
  202. int i;
  203. mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
  204. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  205. bus_isa, 0, apicid, 0);
  206. mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  207. bus_isa, 1, apicid, 1);
  208. mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
  209. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  210. bus_isa, 0, apicid, 2);
  211. for (i = 3; i < 16; i++) {
  212. /*
  213. * Do not write ISA interrupt entry if it is already occupied
  214. * by the platform devices.
  215. */
  216. if (isa_irq_occupied[i])
  217. continue;
  218. mp_write_intsrc(mc, MP_INT,
  219. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  220. bus_isa, i, apicid, i);
  221. }
  222. }
  223. /*
  224. * Check duplicated I/O interrupt assignment table entry, to make sure
  225. * there is only one entry with the given bus, device and interrupt pin.
  226. */
  227. static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
  228. int entry_num, int bus, int device, int pin)
  229. {
  230. struct mpc_config_intsrc *intsrc = intsrc_base;
  231. int i;
  232. for (i = 0; i < entry_num; i++) {
  233. if (intsrc->mpc_srcbus == bus &&
  234. intsrc->mpc_srcbusirq == ((device << 2) | (pin - 1)))
  235. break;
  236. intsrc++;
  237. }
  238. return (i == entry_num) ? false : true;
  239. }
  240. /* TODO: move this to driver model */
  241. __weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
  242. {
  243. /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */
  244. return pirq + 16;
  245. }
  246. static int mptable_add_intsrc(struct mp_config_table *mc,
  247. int bus_isa, int apicid)
  248. {
  249. struct mpc_config_intsrc *intsrc_base;
  250. int intsrc_entries = 0;
  251. const void *blob = gd->fdt_blob;
  252. struct udevice *dev;
  253. int len, count;
  254. const u32 *cell;
  255. int i, ret;
  256. ret = uclass_first_device_err(UCLASS_IRQ, &dev);
  257. if (ret && ret != -ENODEV) {
  258. debug("%s: Cannot find irq router node\n", __func__);
  259. return ret;
  260. }
  261. /* Get I/O interrupt information from device tree */
  262. cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
  263. &len);
  264. if (!cell)
  265. return -ENOENT;
  266. if ((len % sizeof(struct pirq_routing)) == 0)
  267. count = len / sizeof(struct pirq_routing);
  268. else
  269. return -EINVAL;
  270. intsrc_base = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
  271. for (i = 0; i < count; i++) {
  272. struct pirq_routing pr;
  273. int bus, dev, func;
  274. int dstirq;
  275. pr.bdf = fdt_addr_to_cpu(cell[0]);
  276. pr.pin = fdt_addr_to_cpu(cell[1]);
  277. pr.pirq = fdt_addr_to_cpu(cell[2]);
  278. bus = PCI_BUS(pr.bdf);
  279. dev = PCI_DEV(pr.bdf);
  280. func = PCI_FUNC(pr.bdf);
  281. if (check_dup_entry(intsrc_base, intsrc_entries,
  282. bus, dev, pr.pin)) {
  283. debug("found entry for bus %d device %d INT%c, skipping\n",
  284. bus, dev, 'A' + pr.pin - 1);
  285. cell += sizeof(struct pirq_routing) / sizeof(u32);
  286. continue;
  287. }
  288. dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq);
  289. /*
  290. * For PIRQ which is connected to I/O APIC interrupt pin#0-15,
  291. * mark it as occupied so that we can skip it later.
  292. */
  293. if (dstirq < 16)
  294. isa_irq_occupied[dstirq] = true;
  295. mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin,
  296. apicid, dstirq);
  297. intsrc_entries++;
  298. cell += sizeof(struct pirq_routing) / sizeof(u32);
  299. }
  300. /* Legacy Interrupts */
  301. debug("Writing ISA IRQs\n");
  302. mptable_add_isa_interrupts(mc, bus_isa, apicid, 0);
  303. return 0;
  304. }
  305. static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
  306. {
  307. mp_write_lintsrc(mc, MP_EXTINT,
  308. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  309. bus_isa, 0, MP_APIC_ALL, 0);
  310. mp_write_lintsrc(mc, MP_NMI,
  311. MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
  312. bus_isa, 0, MP_APIC_ALL, 1);
  313. }
  314. ulong write_mp_table(ulong addr)
  315. {
  316. struct mp_config_table *mc;
  317. int ioapic_id, ioapic_ver;
  318. int bus_isa = 0xff;
  319. int ret;
  320. ulong end;
  321. /* 16 byte align the table address */
  322. addr = ALIGN(addr, 16);
  323. /* Write floating table */
  324. mc = mp_write_floating_table((struct mp_floating_table *)addr);
  325. /* Write configuration table header */
  326. mp_config_table_init(mc);
  327. /* Write processor entry */
  328. mp_write_processor(mc);
  329. /* Write bus entry */
  330. mp_write_bus(mc, bus_isa, BUSTYPE_ISA);
  331. /* Write I/O APIC entry */
  332. ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
  333. ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
  334. mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
  335. /* Write I/O interrupt assignment entry */
  336. ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
  337. if (ret)
  338. debug("Failed to write I/O interrupt assignment table\n");
  339. /* Write local interrupt assignment entry */
  340. mptable_add_lintsrc(mc, bus_isa);
  341. /* Finalize the MP table */
  342. end = mptable_finalize(mc);
  343. return end;
  344. }