lapic.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot file of same name
  4. *
  5. * Copyright (C) 2008-2009 coresystems GmbH
  6. * Copyright (C) 2014 Google, Inc
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/lapic.h>
  11. #include <asm/msr.h>
  12. #include <asm/msr-index.h>
  13. #include <asm/post.h>
  14. unsigned long lapic_read(unsigned long reg)
  15. {
  16. return readl(LAPIC_DEFAULT_BASE + reg);
  17. }
  18. #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
  19. sizeof(*(ptr))))
  20. struct __xchg_dummy { unsigned long a[100]; };
  21. #define __xg(x) ((struct __xchg_dummy *)(x))
  22. /*
  23. * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
  24. *
  25. * Note 2: xchg has side effect, so that attribute volatile is necessary,
  26. * but generally the primitive is invalid, *ptr is output argument.
  27. */
  28. static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
  29. int size)
  30. {
  31. switch (size) {
  32. case 1:
  33. __asm__ __volatile__("xchgb %b0,%1"
  34. : "=q" (x)
  35. : "m" (*__xg(ptr)), "0" (x)
  36. : "memory");
  37. break;
  38. case 2:
  39. __asm__ __volatile__("xchgw %w0,%1"
  40. : "=r" (x)
  41. : "m" (*__xg(ptr)), "0" (x)
  42. : "memory");
  43. break;
  44. case 4:
  45. __asm__ __volatile__("xchgl %0,%1"
  46. : "=r" (x)
  47. : "m" (*__xg(ptr)), "0" (x)
  48. : "memory");
  49. break;
  50. }
  51. return x;
  52. }
  53. void lapic_write(unsigned long reg, unsigned long v)
  54. {
  55. (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
  56. }
  57. void enable_lapic(void)
  58. {
  59. if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
  60. msr_t msr;
  61. msr = msr_read(MSR_IA32_APICBASE);
  62. msr.hi &= 0xffffff00;
  63. msr.lo |= MSR_IA32_APICBASE_ENABLE;
  64. msr.lo &= ~MSR_IA32_APICBASE_BASE;
  65. msr.lo |= LAPIC_DEFAULT_BASE;
  66. msr_write(MSR_IA32_APICBASE, msr);
  67. }
  68. }
  69. void disable_lapic(void)
  70. {
  71. if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
  72. msr_t msr;
  73. msr = msr_read(MSR_IA32_APICBASE);
  74. msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
  75. msr_write(MSR_IA32_APICBASE, msr);
  76. }
  77. }
  78. unsigned long lapicid(void)
  79. {
  80. return lapic_read(LAPIC_ID) >> 24;
  81. }
  82. static void lapic_wait_icr_idle(void)
  83. {
  84. do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
  85. }
  86. int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
  87. {
  88. int timeout;
  89. unsigned long status;
  90. int result;
  91. lapic_wait_icr_idle();
  92. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  93. lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
  94. timeout = 0;
  95. do {
  96. status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
  97. } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
  98. result = -1;
  99. if (status == LAPIC_ICR_RR_VALID) {
  100. *pvalue = lapic_read(LAPIC_RRR);
  101. result = 0;
  102. }
  103. return result;
  104. }
  105. void lapic_setup(void)
  106. {
  107. /* Only Pentium Pro and later have those MSR stuff */
  108. debug("Setting up local apic: ");
  109. /* Enable the local apic */
  110. enable_lapic();
  111. /* Set Task Priority to 'accept all' */
  112. lapic_write(LAPIC_TASKPRI,
  113. lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
  114. /* Put the local apic in virtual wire mode */
  115. lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
  116. ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
  117. lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
  118. ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
  119. LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
  120. LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
  121. LAPIC_DELIVERY_MODE_MASK)) |
  122. (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
  123. LAPIC_DELIVERY_MODE_EXTINT));
  124. lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
  125. ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
  126. LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
  127. LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
  128. LAPIC_DELIVERY_MODE_MASK)) |
  129. (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
  130. LAPIC_DELIVERY_MODE_NMI));
  131. debug("apic_id: 0x%02lx, ", lapicid());
  132. debug("done.\n");
  133. post_code(POST_LAPIC);
  134. }