call32.S 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <asm/global_data.h>
  7. #include <asm/msr-index.h>
  8. #include <asm/processor-flags.h>
  9. /*
  10. * rdi - 32-bit code segment selector
  11. * rsi - target address
  12. * rdx - table address (0 if none)
  13. */
  14. .code64
  15. .globl cpu_call32
  16. cpu_call32:
  17. cli
  18. /* Save table pointer */
  19. mov %edx, %ebx
  20. /*
  21. * Debugging option, this outputs characters to the console UART
  22. * mov $0x3f8,%edx
  23. * mov $'a',%al
  24. * out %al,(%dx)
  25. */
  26. pushf
  27. push %rdi /* 32-bit code segment */
  28. lea compat(%rip), %rax
  29. push %rax
  30. .byte 0x48 /* REX prefix to force 64-bit far return */
  31. retf
  32. .code32
  33. compat:
  34. /*
  35. * We are now in compatibility mode with a default operand size of
  36. * 32 bits. First disable paging.
  37. */
  38. movl %cr0, %eax
  39. andl $~X86_CR0_PG, %eax
  40. movl %eax, %cr0
  41. /* Invalidate TLB */
  42. xorl %eax, %eax
  43. movl %eax, %cr3
  44. /* Disable Long mode in EFER (Extended Feature Enable Register) */
  45. movl $MSR_EFER, %ecx
  46. rdmsr
  47. btr $_EFER_LME, %eax
  48. wrmsr
  49. /* Set up table pointer for _x86boot_start */
  50. mov %ebx, %ecx
  51. /* Jump to the required target */
  52. pushl %edi /* 32-bit code segment */
  53. pushl %esi /* 32-bit target address */
  54. retf