fu540-c000.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2018-2019 SiFive, Inc */
  3. /dts-v1/;
  4. #include <dt-bindings/clock/sifive-fu540-prci.h>
  5. / {
  6. #address-cells = <2>;
  7. #size-cells = <2>;
  8. compatible = "sifive,fu540-c000", "sifive,fu540";
  9. aliases {
  10. serial0 = &uart0;
  11. serial1 = &uart1;
  12. ethernet0 = &eth0;
  13. };
  14. chosen {
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu0: cpu@0 {
  20. compatible = "sifive,e51", "sifive,rocket0", "riscv";
  21. device_type = "cpu";
  22. i-cache-block-size = <64>;
  23. i-cache-sets = <128>;
  24. i-cache-size = <16384>;
  25. reg = <0>;
  26. riscv,isa = "rv64imac";
  27. status = "disabled";
  28. cpu0_intc: interrupt-controller {
  29. #interrupt-cells = <1>;
  30. compatible = "riscv,cpu-intc";
  31. interrupt-controller;
  32. };
  33. };
  34. cpu1: cpu@1 {
  35. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  36. d-cache-block-size = <64>;
  37. d-cache-sets = <64>;
  38. d-cache-size = <32768>;
  39. d-tlb-sets = <1>;
  40. d-tlb-size = <32>;
  41. device_type = "cpu";
  42. i-cache-block-size = <64>;
  43. i-cache-sets = <64>;
  44. i-cache-size = <32768>;
  45. i-tlb-sets = <1>;
  46. i-tlb-size = <32>;
  47. mmu-type = "riscv,sv39";
  48. reg = <1>;
  49. riscv,isa = "rv64imafdc";
  50. tlb-split;
  51. cpu1_intc: interrupt-controller {
  52. #interrupt-cells = <1>;
  53. compatible = "riscv,cpu-intc";
  54. interrupt-controller;
  55. };
  56. };
  57. cpu2: cpu@2 {
  58. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  59. d-cache-block-size = <64>;
  60. d-cache-sets = <64>;
  61. d-cache-size = <32768>;
  62. d-tlb-sets = <1>;
  63. d-tlb-size = <32>;
  64. device_type = "cpu";
  65. i-cache-block-size = <64>;
  66. i-cache-sets = <64>;
  67. i-cache-size = <32768>;
  68. i-tlb-sets = <1>;
  69. i-tlb-size = <32>;
  70. mmu-type = "riscv,sv39";
  71. reg = <2>;
  72. riscv,isa = "rv64imafdc";
  73. tlb-split;
  74. cpu2_intc: interrupt-controller {
  75. #interrupt-cells = <1>;
  76. compatible = "riscv,cpu-intc";
  77. interrupt-controller;
  78. };
  79. };
  80. cpu3: cpu@3 {
  81. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  82. d-cache-block-size = <64>;
  83. d-cache-sets = <64>;
  84. d-cache-size = <32768>;
  85. d-tlb-sets = <1>;
  86. d-tlb-size = <32>;
  87. device_type = "cpu";
  88. i-cache-block-size = <64>;
  89. i-cache-sets = <64>;
  90. i-cache-size = <32768>;
  91. i-tlb-sets = <1>;
  92. i-tlb-size = <32>;
  93. mmu-type = "riscv,sv39";
  94. reg = <3>;
  95. riscv,isa = "rv64imafdc";
  96. tlb-split;
  97. cpu3_intc: interrupt-controller {
  98. #interrupt-cells = <1>;
  99. compatible = "riscv,cpu-intc";
  100. interrupt-controller;
  101. };
  102. };
  103. cpu4: cpu@4 {
  104. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  105. d-cache-block-size = <64>;
  106. d-cache-sets = <64>;
  107. d-cache-size = <32768>;
  108. d-tlb-sets = <1>;
  109. d-tlb-size = <32>;
  110. device_type = "cpu";
  111. i-cache-block-size = <64>;
  112. i-cache-sets = <64>;
  113. i-cache-size = <32768>;
  114. i-tlb-sets = <1>;
  115. i-tlb-size = <32>;
  116. mmu-type = "riscv,sv39";
  117. reg = <4>;
  118. riscv,isa = "rv64imafdc";
  119. tlb-split;
  120. cpu4_intc: interrupt-controller {
  121. #interrupt-cells = <1>;
  122. compatible = "riscv,cpu-intc";
  123. interrupt-controller;
  124. };
  125. };
  126. };
  127. soc {
  128. #address-cells = <2>;
  129. #size-cells = <2>;
  130. compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
  131. ranges;
  132. plic0: interrupt-controller@c000000 {
  133. #interrupt-cells = <1>;
  134. compatible = "sifive,plic-1.0.0";
  135. reg = <0x0 0xc000000 0x0 0x4000000>;
  136. riscv,ndev = <53>;
  137. interrupt-controller;
  138. interrupts-extended = <
  139. &cpu0_intc 0xffffffff
  140. &cpu1_intc 0xffffffff &cpu1_intc 9
  141. &cpu2_intc 0xffffffff &cpu2_intc 9
  142. &cpu3_intc 0xffffffff &cpu3_intc 9
  143. &cpu4_intc 0xffffffff &cpu4_intc 9>;
  144. };
  145. prci: clock-controller@10000000 {
  146. compatible = "sifive,fu540-c000-prci";
  147. reg = <0x0 0x10000000 0x0 0x1000>;
  148. clocks = <&hfclk>, <&rtcclk>;
  149. #clock-cells = <1>;
  150. };
  151. uart0: serial@10010000 {
  152. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  153. reg = <0x0 0x10010000 0x0 0x1000>;
  154. interrupt-parent = <&plic0>;
  155. interrupts = <4>;
  156. clocks = <&prci PRCI_CLK_TLCLK>;
  157. status = "disabled";
  158. };
  159. uart1: serial@10011000 {
  160. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  161. reg = <0x0 0x10011000 0x0 0x1000>;
  162. interrupt-parent = <&plic0>;
  163. interrupts = <5>;
  164. clocks = <&prci PRCI_CLK_TLCLK>;
  165. status = "disabled";
  166. };
  167. i2c0: i2c@10030000 {
  168. compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
  169. reg = <0x0 0x10030000 0x0 0x1000>;
  170. interrupt-parent = <&plic0>;
  171. interrupts = <50>;
  172. clocks = <&prci PRCI_CLK_TLCLK>;
  173. reg-shift = <2>;
  174. reg-io-width = <1>;
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. status = "disabled";
  178. };
  179. qspi0: spi@10040000 {
  180. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  181. reg = <0x0 0x10040000 0x0 0x1000
  182. 0x0 0x20000000 0x0 0x10000000>;
  183. interrupt-parent = <&plic0>;
  184. interrupts = <51>;
  185. clocks = <&prci PRCI_CLK_TLCLK>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. status = "disabled";
  189. };
  190. qspi1: spi@10041000 {
  191. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  192. reg = <0x0 0x10041000 0x0 0x1000
  193. 0x0 0x30000000 0x0 0x10000000>;
  194. interrupt-parent = <&plic0>;
  195. interrupts = <52>;
  196. clocks = <&prci PRCI_CLK_TLCLK>;
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. status = "disabled";
  200. };
  201. qspi2: spi@10050000 {
  202. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  203. reg = <0x0 0x10050000 0x0 0x1000>;
  204. interrupt-parent = <&plic0>;
  205. interrupts = <6>;
  206. clocks = <&prci PRCI_CLK_TLCLK>;
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. status = "disabled";
  210. };
  211. eth0: ethernet@10090000 {
  212. compatible = "sifive,fu540-c000-gem";
  213. interrupt-parent = <&plic0>;
  214. interrupts = <53>;
  215. reg = <0x0 0x10090000 0x0 0x2000
  216. 0x0 0x100a0000 0x0 0x1000>;
  217. local-mac-address = [00 00 00 00 00 00];
  218. clock-names = "pclk", "hclk";
  219. clocks = <&prci PRCI_CLK_GEMGXLPLL>,
  220. <&prci PRCI_CLK_GEMGXLPLL>;
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. status = "disabled";
  224. };
  225. pwm0: pwm@10020000 {
  226. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  227. reg = <0x0 0x10020000 0x0 0x1000>;
  228. interrupt-parent = <&plic0>;
  229. interrupts = <42 43 44 45>;
  230. clocks = <&prci PRCI_CLK_TLCLK>;
  231. #pwm-cells = <3>;
  232. status = "disabled";
  233. };
  234. pwm1: pwm@10021000 {
  235. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  236. reg = <0x0 0x10021000 0x0 0x1000>;
  237. interrupt-parent = <&plic0>;
  238. interrupts = <46 47 48 49>;
  239. clocks = <&prci PRCI_CLK_TLCLK>;
  240. #pwm-cells = <3>;
  241. status = "disabled";
  242. };
  243. };
  244. };