cpu.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015
  4. * Purna Chandra Mandal <purna.mandal@microchip.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <mach/pic32.h>
  11. #include <mach/ddr.h>
  12. #include <dt-bindings/clock/microchip,clock.h>
  13. /* Flash prefetch */
  14. #define PRECON 0x00
  15. /* Flash ECCCON */
  16. #define ECC_MASK 0x03
  17. #define ECC_SHIFT 4
  18. #define CLK_MHZ(x) ((x) / 1000000)
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static ulong rate(int id)
  21. {
  22. int ret;
  23. struct udevice *dev;
  24. struct clk clk;
  25. ulong rate;
  26. ret = uclass_get_device(UCLASS_CLK, 0, &dev);
  27. if (ret) {
  28. printf("clk-uclass not found\n");
  29. return 0;
  30. }
  31. clk.id = id;
  32. ret = clk_request(dev, &clk);
  33. if (ret < 0)
  34. return ret;
  35. rate = clk_get_rate(&clk);
  36. clk_free(&clk);
  37. return rate;
  38. }
  39. static ulong clk_get_cpu_rate(void)
  40. {
  41. return rate(PB7CLK);
  42. }
  43. /* initialize prefetch module related to cpu_clk */
  44. static void prefetch_init(void)
  45. {
  46. struct pic32_reg_atomic *regs;
  47. const void __iomem *base;
  48. int v, nr_waits;
  49. ulong rate;
  50. /* cpu frequency in MHZ */
  51. rate = clk_get_cpu_rate() / 1000000;
  52. /* get flash ECC type */
  53. base = pic32_get_syscfg_base();
  54. v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
  55. if (v < 2) {
  56. if (rate < 66)
  57. nr_waits = 0;
  58. else if (rate < 133)
  59. nr_waits = 1;
  60. else
  61. nr_waits = 2;
  62. } else {
  63. if (rate <= 83)
  64. nr_waits = 0;
  65. else if (rate <= 166)
  66. nr_waits = 1;
  67. else
  68. nr_waits = 2;
  69. }
  70. regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
  71. writel(nr_waits, &regs->raw);
  72. /* Enable prefetch for all */
  73. writel(0x30, &regs->set);
  74. iounmap(regs);
  75. }
  76. /* arch specific CPU init after DM */
  77. int arch_cpu_init_dm(void)
  78. {
  79. /* flash prefetch */
  80. prefetch_init();
  81. return 0;
  82. }
  83. /* Un-gate DDR2 modules (gated by default) */
  84. static void ddr2_pmd_ungate(void)
  85. {
  86. void __iomem *regs;
  87. regs = pic32_get_syscfg_base();
  88. writel(0, regs + PMD7);
  89. }
  90. /* initialize the DDR2 Controller and DDR2 PHY */
  91. int dram_init(void)
  92. {
  93. ddr2_pmd_ungate();
  94. ddr2_phy_init();
  95. ddr2_ctrl_init();
  96. gd->ram_size = ddr2_calculate_size();
  97. return 0;
  98. }
  99. int misc_init_r(void)
  100. {
  101. set_io_port_base(0);
  102. return 0;
  103. }
  104. #ifdef CONFIG_DISPLAY_BOARDINFO
  105. const char *get_core_name(void)
  106. {
  107. u32 proc_id;
  108. const char *str;
  109. proc_id = read_c0_prid();
  110. switch (proc_id) {
  111. case 0x19e28:
  112. str = "PIC32MZ[DA]";
  113. break;
  114. default:
  115. str = "UNKNOWN";
  116. }
  117. return str;
  118. }
  119. #endif
  120. #ifdef CONFIG_CMD_CLK
  121. int soc_clk_dump(void)
  122. {
  123. int i;
  124. printf("PLL Speed: %lu MHz\n",
  125. CLK_MHZ(rate(PLLCLK)));
  126. printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
  127. printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
  128. for (i = PB1CLK; i <= PB7CLK; i++)
  129. printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
  130. CLK_MHZ(rate(i)));
  131. for (i = REF1CLK; i <= REF5CLK; i++)
  132. printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
  133. CLK_MHZ(rate(i)));
  134. return 0;
  135. }
  136. #endif