anole-c810.dts 1.7 KB

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  1. /dts-v1/;
  2. / {
  3. model = "csky anole_c810smp";
  4. compatible = "csky,anole_c810smp";
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. memory {
  8. device_type = "memory";
  9. reg = <0x40000000 0x20000000>;
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. timebase-frequency = <50000000>;
  15. cpu@0 {
  16. device_type = "cpu";
  17. reg = <0>;
  18. status = "okay";
  19. compatible = "csky";
  20. csky,isa = "Unknown";
  21. };
  22. };
  23. soc {
  24. #address-cells = <1>;
  25. #size-cells = <1>;
  26. compatible = "simple-bus";
  27. ranges;
  28. intc: interrupt-controller {
  29. compatible = "csky,mpintc";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. };
  33. dummy_clk_ahb: dummy-clk-ahb {
  34. compatible = "fixed-clock";
  35. clock-frequency = <250000000>;
  36. clock-output-names = "dummy_clk_ahb";
  37. #clock-cells = <0>;
  38. };
  39. serial@bff73400 {
  40. compatible = "snps,dw-apb-uart";
  41. reg = <0xbff73400 0x400>;
  42. interrupt-parent = <&intc>;
  43. interrupts = <39>;
  44. clock-frequency = <62500000>;
  45. clock-names = "baudclk";
  46. reg-shift = <2>;
  47. reg-io-width = <4>;
  48. };
  49. mmc: mmc0@bffb0000 {
  50. compatible = "snps,dw-mshc";
  51. reg = <0xbffb0000 0x400>;
  52. bus-width = <8>;
  53. clocks = <&dummy_clk_ahb>, <&dummy_clk_ahb>;
  54. clock-names = "biu", "ciu";
  55. max-frequency = <25000000>;
  56. };
  57. };
  58. chosen {
  59. bootargs = "console=ttyS0,115200";
  60. stdout-path = "/soc/serial@bff73400:115200";
  61. };
  62. };