slcr.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2013 - 2017 Xilinx Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <malloc.h>
  8. #include <asm/arch/hardware.h>
  9. #include <asm/arch/sys_proto.h>
  10. #define SLCR_LOCK_MAGIC 0x767B
  11. #define SLCR_UNLOCK_MAGIC 0xDF0D
  12. #define SLCR_NAND_L2_SEL 0x10
  13. #define SLCR_NAND_L2_SEL_MASK 0x1F
  14. #define SLCR_USB_L1_SEL 0x04
  15. #define SLCR_IDCODE_MASK 0x1F000
  16. #define SLCR_IDCODE_SHIFT 12
  17. /*
  18. * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
  19. *
  20. * @peri_name: Name of the peripheral for checking MIO status
  21. * @get_pins: Pointer to array of get pin for this peripheral
  22. * @num_pins: Number of pins for this peripheral
  23. * @mask: Mask value
  24. * @check_val: Required check value to get the status of periph
  25. */
  26. struct zynq_slcr_mio_get_status {
  27. const char *peri_name;
  28. const int *get_pins;
  29. int num_pins;
  30. u32 mask;
  31. u32 check_val;
  32. };
  33. static const int nand8_pins[] = {
  34. 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
  35. };
  36. static const int nand16_pins[] = {
  37. 16, 17, 18, 19, 20, 21, 22, 23
  38. };
  39. static const int usb0_pins[] = {
  40. 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
  41. };
  42. static const int usb1_pins[] = {
  43. 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
  44. };
  45. static const struct zynq_slcr_mio_get_status mio_periphs[] = {
  46. {
  47. "nand8",
  48. nand8_pins,
  49. ARRAY_SIZE(nand8_pins),
  50. SLCR_NAND_L2_SEL_MASK,
  51. SLCR_NAND_L2_SEL,
  52. },
  53. {
  54. "nand16",
  55. nand16_pins,
  56. ARRAY_SIZE(nand16_pins),
  57. SLCR_NAND_L2_SEL_MASK,
  58. SLCR_NAND_L2_SEL,
  59. },
  60. {
  61. "usb0",
  62. usb0_pins,
  63. ARRAY_SIZE(usb0_pins),
  64. SLCR_USB_L1_SEL,
  65. SLCR_USB_L1_SEL,
  66. },
  67. {
  68. "usb1",
  69. usb1_pins,
  70. ARRAY_SIZE(usb1_pins),
  71. SLCR_USB_L1_SEL,
  72. SLCR_USB_L1_SEL,
  73. },
  74. };
  75. static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
  76. void zynq_slcr_lock(void)
  77. {
  78. if (!slcr_lock) {
  79. writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
  80. slcr_lock = 1;
  81. }
  82. }
  83. void zynq_slcr_unlock(void)
  84. {
  85. if (slcr_lock) {
  86. writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
  87. slcr_lock = 0;
  88. }
  89. }
  90. /* Reset the entire system */
  91. void zynq_slcr_cpu_reset(void)
  92. {
  93. /*
  94. * Unlock the SLCR then reset the system.
  95. * Note that this seems to require raw i/o
  96. * functions or there's a lockup?
  97. */
  98. zynq_slcr_unlock();
  99. /*
  100. * Clear 0x0F000000 bits of reboot status register to workaround
  101. * the FSBL not loading the bitstream after soft-reboot
  102. * This is a temporary solution until we know more.
  103. */
  104. clrbits_le32(&slcr_base->reboot_status, 0xF000000);
  105. writel(1, &slcr_base->pss_rst_ctrl);
  106. }
  107. void zynq_slcr_devcfg_disable(void)
  108. {
  109. u32 reg_val;
  110. zynq_slcr_unlock();
  111. /* Disable AXI interface by asserting FPGA resets */
  112. writel(0xF, &slcr_base->fpga_rst_ctrl);
  113. /* Disable Level shifters before setting PS-PL */
  114. reg_val = readl(&slcr_base->lvl_shftr_en);
  115. reg_val &= ~0xF;
  116. writel(reg_val, &slcr_base->lvl_shftr_en);
  117. /* Set Level Shifters DT618760 */
  118. writel(0xA, &slcr_base->lvl_shftr_en);
  119. zynq_slcr_lock();
  120. }
  121. void zynq_slcr_devcfg_enable(void)
  122. {
  123. zynq_slcr_unlock();
  124. /* Set Level Shifters DT618760 */
  125. writel(0xF, &slcr_base->lvl_shftr_en);
  126. /* Enable AXI interface by de-asserting FPGA resets */
  127. writel(0x0, &slcr_base->fpga_rst_ctrl);
  128. zynq_slcr_lock();
  129. }
  130. u32 zynq_slcr_get_boot_mode(void)
  131. {
  132. /* Get the bootmode register value */
  133. return readl(&slcr_base->boot_mode);
  134. }
  135. u32 zynq_slcr_get_idcode(void)
  136. {
  137. return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
  138. SLCR_IDCODE_SHIFT;
  139. }
  140. /*
  141. * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
  142. *
  143. * @periph: Name of the peripheral
  144. *
  145. * Returns count to indicate the number of pins configured for the
  146. * given @periph.
  147. */
  148. int zynq_slcr_get_mio_pin_status(const char *periph)
  149. {
  150. const struct zynq_slcr_mio_get_status *mio_ptr;
  151. int val, j;
  152. int mio = 0;
  153. u32 i;
  154. for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
  155. if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
  156. mio_ptr = &mio_periphs[i];
  157. for (j = 0; j < mio_ptr->num_pins; j++) {
  158. val = readl(&slcr_base->mio_pin
  159. [mio_ptr->get_pins[j]]);
  160. if ((val & mio_ptr->mask) == mio_ptr->check_val)
  161. mio++;
  162. }
  163. break;
  164. }
  165. }
  166. return mio;
  167. }