ddrc.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/arch/hardware.h>
  10. #ifndef CONFIG_ZYNQ_DDRC_INIT
  11. void zynq_ddrc_init(void) {}
  12. #else
  13. /* Control regsiter bitfield definitions */
  14. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
  15. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
  16. #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1
  17. /* ECC scrub regsiter definitions */
  18. #define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7
  19. #define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4
  20. void zynq_ddrc_init(void)
  21. {
  22. u32 width, ecctype;
  23. width = readl(&ddrc_base->ddrc_ctrl);
  24. width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
  25. ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
  26. ecctype = (readl(&ddrc_base->ecc_scrub) &
  27. ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
  28. /* ECC is enabled when memory is in 16bit mode and it is enabled */
  29. if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
  30. (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
  31. puts("ECC enabled ");
  32. /*
  33. * Clear the first 1MB because it is not initialized from
  34. * first stage bootloader. To get ECC to work all memory has
  35. * been initialized by writing any value.
  36. */
  37. /* cppcheck-suppress nullPointer */
  38. memset((void *)0, 0, 1 * 1024 * 1024);
  39. } else {
  40. puts("ECC disabled ");
  41. }
  42. }
  43. #endif