clk.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
  4. * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <asm/arch/clk.h>
  10. DECLARE_GLOBAL_DATA_PTR;
  11. static const char * const clk_names[clk_max] = {
  12. "armpll", "ddrpll", "iopll",
  13. "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  14. "ddr2x", "ddr3x", "dci",
  15. "lqspi", "smc", "pcap", "gem0", "gem1",
  16. "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  17. "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
  18. "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
  19. "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
  20. "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
  21. "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
  22. "smc_aper", "swdt", "dbg_trc", "dbg_apb"
  23. };
  24. /**
  25. * set_cpu_clk_info() - Setup clock information
  26. *
  27. * This function is called from common code after relocation and sets up the
  28. * clock information.
  29. */
  30. int set_cpu_clk_info(void)
  31. {
  32. struct clk clk;
  33. struct udevice *dev;
  34. ulong rate;
  35. int i, ret;
  36. ret = uclass_get_device_by_driver(UCLASS_CLK,
  37. DM_GET_DRIVER(zynq_clk), &dev);
  38. if (ret)
  39. return ret;
  40. for (i = 0; i < 2; i++) {
  41. clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
  42. ret = clk_request(dev, &clk);
  43. if (ret < 0)
  44. return ret;
  45. rate = clk_get_rate(&clk) / 1000000;
  46. if (i)
  47. gd->bd->bi_ddr_freq = rate;
  48. else
  49. gd->bd->bi_arm_freq = rate;
  50. clk_free(&clk);
  51. }
  52. gd->bd->bi_dsp_freq = 0;
  53. return 0;
  54. }
  55. /**
  56. * soc_clk_dump() - Print clock frequencies
  57. * Returns zero on success
  58. *
  59. * Implementation for the clk dump command.
  60. */
  61. int soc_clk_dump(void)
  62. {
  63. struct udevice *dev;
  64. int i, ret;
  65. ret = uclass_get_device_by_driver(UCLASS_CLK,
  66. DM_GET_DRIVER(zynq_clk), &dev);
  67. if (ret)
  68. return ret;
  69. printf("clk\t\tfrequency\n");
  70. for (i = 0; i < clk_max; i++) {
  71. const char *name = clk_names[i];
  72. if (name) {
  73. struct clk clk;
  74. unsigned long rate;
  75. clk.id = i;
  76. ret = clk_request(dev, &clk);
  77. if (ret < 0)
  78. return ret;
  79. rate = clk_get_rate(&clk);
  80. clk_free(&clk);
  81. if ((rate == (unsigned long)-ENOSYS) ||
  82. (rate == (unsigned long)-ENXIO))
  83. printf("%10s%20s\n", name, "unknown");
  84. else
  85. printf("%10s%20lu\n", name, rate);
  86. }
  87. }
  88. return 0;
  89. }