clock-snapdragon.h 1001 B

123456789101112131415161718192021222324252627282930313233343536373839404142434445
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Qualcomm APQ8016, APQ8096
  4. *
  5. * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  6. */
  7. #ifndef _CLOCK_SNAPDRAGON_H
  8. #define _CLOCK_SNAPDRAGON_H
  9. #define CFG_CLK_SRC_CXO (0 << 8)
  10. #define CFG_CLK_SRC_GPLL0 (1 << 8)
  11. #define CFG_CLK_SRC_MASK (7 << 8)
  12. struct pll_vote_clk {
  13. uintptr_t status;
  14. int status_bit;
  15. uintptr_t ena_vote;
  16. int vote_bit;
  17. };
  18. struct vote_clk {
  19. uintptr_t cbcr_reg;
  20. uintptr_t ena_vote;
  21. int vote_bit;
  22. };
  23. struct bcr_regs {
  24. uintptr_t cfg_rcgr;
  25. uintptr_t cmd_rcgr;
  26. uintptr_t M;
  27. uintptr_t N;
  28. uintptr_t D;
  29. };
  30. struct msm_clk_priv {
  31. phys_addr_t base;
  32. };
  33. void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
  34. void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
  35. void clk_enable_cbc(phys_addr_t cbcr);
  36. void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
  37. void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
  38. int div, int m, int n, int source);
  39. #endif