clock-snapdragon.c 3.5 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause
  2. /*
  3. * Clock drivers for Qualcomm APQ8016, APQ8096
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. *
  7. * Based on Little Kernel driver, simplified
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <asm/io.h>
  14. #include <linux/bitops.h>
  15. #include "clock-snapdragon.h"
  16. /* CBCR register fields */
  17. #define CBCR_BRANCH_ENABLE_BIT BIT(0)
  18. #define CBCR_BRANCH_OFF_BIT BIT(31)
  19. extern ulong msm_set_rate(struct clk *clk, ulong rate);
  20. /* Enable clock controlled by CBC soft macro */
  21. void clk_enable_cbc(phys_addr_t cbcr)
  22. {
  23. setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
  24. while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
  25. ;
  26. }
  27. void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
  28. {
  29. if (readl(base + gpll0->status) & gpll0->status_bit)
  30. return; /* clock already enabled */
  31. setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
  32. while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
  33. ;
  34. }
  35. #define BRANCH_ON_VAL (0)
  36. #define BRANCH_NOC_FSM_ON_VAL BIT(29)
  37. #define BRANCH_CHECK_MASK GENMASK(31, 28)
  38. void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
  39. {
  40. u32 val;
  41. setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
  42. do {
  43. val = readl(base + vclk->cbcr_reg);
  44. val &= BRANCH_CHECK_MASK;
  45. } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
  46. }
  47. #define APPS_CMD_RGCR_UPDATE BIT(0)
  48. /* Update clock command via CMD_RGCR */
  49. void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
  50. {
  51. setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
  52. /* Wait for frequency to be updated. */
  53. while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
  54. ;
  55. }
  56. #define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
  57. #define CFG_MASK 0x3FFF
  58. #define CFG_DIVIDER_MASK 0x1F
  59. /* root set rate for clocks with half integer and MND divider */
  60. void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
  61. int div, int m, int n, int source)
  62. {
  63. u32 cfg;
  64. /* M value for MND divider. */
  65. u32 m_val = m;
  66. /* NOT(N-M) value for MND divider. */
  67. u32 n_val = ~((n) - (m)) * !!(n);
  68. /* NOT 2D value for MND divider. */
  69. u32 d_val = ~(n);
  70. /* Program MND values */
  71. writel(m_val, base + regs->M);
  72. writel(n_val, base + regs->N);
  73. writel(d_val, base + regs->D);
  74. /* setup src select and divider */
  75. cfg = readl(base + regs->cfg_rcgr);
  76. cfg &= ~CFG_MASK;
  77. cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
  78. /* Set the divider; HW permits fraction dividers (+0.5), but
  79. for simplicity, we will support integers only */
  80. if (div)
  81. cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
  82. if (n_val)
  83. cfg |= CFG_MODE_DUAL_EDGE;
  84. writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
  85. /* Inform h/w to start using the new config. */
  86. clk_bcr_update(base + regs->cmd_rcgr);
  87. }
  88. static int msm_clk_probe(struct udevice *dev)
  89. {
  90. struct msm_clk_priv *priv = dev_get_priv(dev);
  91. priv->base = devfdt_get_addr(dev);
  92. if (priv->base == FDT_ADDR_T_NONE)
  93. return -EINVAL;
  94. return 0;
  95. }
  96. static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
  97. {
  98. return msm_set_rate(clk, rate);
  99. }
  100. static struct clk_ops msm_clk_ops = {
  101. .set_rate = msm_clk_set_rate,
  102. };
  103. static const struct udevice_id msm_clk_ids[] = {
  104. { .compatible = "qcom,gcc-msm8916" },
  105. { .compatible = "qcom,gcc-apq8016" },
  106. { .compatible = "qcom,gcc-msm8996" },
  107. { .compatible = "qcom,gcc-apq8096" },
  108. { }
  109. };
  110. U_BOOT_DRIVER(clk_msm) = {
  111. .name = "clk_msm",
  112. .id = UCLASS_CLK,
  113. .of_match = msm_clk_ids,
  114. .ops = &msm_clk_ops,
  115. .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
  116. .probe = msm_clk_probe,
  117. };