clock-apq8096.c 2.1 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause
  2. /*
  3. * Clock drivers for Qualcomm APQ8096
  4. *
  5. * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
  6. *
  7. * Based on Little Kernel driver, simplified
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <asm/io.h>
  14. #include <linux/bitops.h>
  15. #include "clock-snapdragon.h"
  16. /* GPLL0 clock control registers */
  17. #define GPLL0_STATUS_ACTIVE BIT(30)
  18. #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
  19. static const struct bcr_regs sdc_regs = {
  20. .cfg_rcgr = SDCC2_CFG_RCGR,
  21. .cmd_rcgr = SDCC2_CMD_RCGR,
  22. .M = SDCC2_M,
  23. .N = SDCC2_N,
  24. .D = SDCC2_D,
  25. };
  26. static const struct pll_vote_clk gpll0_vote_clk = {
  27. .status = GPLL0_STATUS,
  28. .status_bit = GPLL0_STATUS_ACTIVE,
  29. .ena_vote = APCS_GPLL_ENA_VOTE,
  30. .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
  31. };
  32. static struct vote_clk gcc_blsp2_ahb_clk = {
  33. .cbcr_reg = BLSP2_AHB_CBCR,
  34. .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
  35. .vote_bit = BIT(15),
  36. };
  37. static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
  38. {
  39. int div = 3;
  40. clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
  41. clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
  42. CFG_CLK_SRC_GPLL0);
  43. clk_enable_gpll0(priv->base, &gpll0_vote_clk);
  44. clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
  45. return rate;
  46. }
  47. static const struct bcr_regs uart2_regs = {
  48. .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
  49. .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
  50. .M = BLSP2_UART2_APPS_M,
  51. .N = BLSP2_UART2_APPS_N,
  52. .D = BLSP2_UART2_APPS_D,
  53. };
  54. static int clk_init_uart(struct msm_clk_priv *priv)
  55. {
  56. /* Enable AHB clock */
  57. clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
  58. /* 7372800 uart block clock @ GPLL0 */
  59. clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
  60. CFG_CLK_SRC_GPLL0);
  61. /* Vote for gpll0 clock */
  62. clk_enable_gpll0(priv->base, &gpll0_vote_clk);
  63. /* Enable core clk */
  64. clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
  65. return 0;
  66. }
  67. ulong msm_set_rate(struct clk *clk, ulong rate)
  68. {
  69. struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  70. switch (clk->id) {
  71. case 0: /* SDC1 */
  72. return clk_init_sdc(priv, rate);
  73. break;
  74. case 4: /*UART2*/
  75. return clk_init_uart(priv);
  76. default:
  77. return 0;
  78. }
  79. }