timer.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * Copyright (C) Marvell International Ltd. and its affiliates
  7. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  8. */
  9. #include <common.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #define UBOOT_CNTR 0 /* counter to use for uboot timer */
  13. /* Timer reload and current value registers */
  14. struct orion5x_tmr_val {
  15. u32 reload; /* Timer reload reg */
  16. u32 val; /* Timer value reg */
  17. };
  18. /* Timer registers */
  19. struct orion5x_tmr_registers {
  20. u32 ctrl; /* Timer control reg */
  21. u32 pad[3];
  22. struct orion5x_tmr_val tmr[2];
  23. u32 wdt_reload;
  24. u32 wdt_val;
  25. };
  26. struct orion5x_tmr_registers *orion5x_tmr_regs =
  27. (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
  28. /*
  29. * ARM Timers Registers Map
  30. */
  31. #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
  32. #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
  33. #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
  34. /*
  35. * ARM Timers Control Register
  36. * CPU_TIMERS_CTRL_REG (CTCR)
  37. */
  38. #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
  39. #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
  40. #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  41. #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  42. #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
  43. #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
  44. #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  45. #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  46. /*
  47. * ARM Timer\Watchdog Reload Register
  48. * CNTMR_RELOAD_REG (TRR)
  49. */
  50. #define TRG_ARM_TIMER_REL_OFFS 0
  51. #define TRG_ARM_TIMER_REL_MASK 0xffffffff
  52. /*
  53. * ARM Timer\Watchdog Register
  54. * CNTMR_VAL_REG (TVRG)
  55. */
  56. #define TVR_ARM_TIMER_OFFS 0
  57. #define TVR_ARM_TIMER_MASK 0xffffffff
  58. #define TVR_ARM_TIMER_MAX 0xffffffff
  59. #define TIMER_LOAD_VAL 0xffffffff
  60. static inline ulong read_timer(void)
  61. {
  62. return readl(CNTMR_VAL_REG(UBOOT_CNTR))
  63. / (CONFIG_SYS_TCLK / 1000);
  64. }
  65. DECLARE_GLOBAL_DATA_PTR;
  66. #define timestamp gd->arch.tbl
  67. #define lastdec gd->arch.lastinc
  68. static ulong get_timer_masked(void)
  69. {
  70. ulong now = read_timer();
  71. if (lastdec >= now) {
  72. /* normal mode */
  73. timestamp += lastdec - now;
  74. } else {
  75. /* we have an overflow ... */
  76. timestamp += lastdec +
  77. (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  78. }
  79. lastdec = now;
  80. return timestamp;
  81. }
  82. ulong get_timer(ulong base)
  83. {
  84. return get_timer_masked() - base;
  85. }
  86. static inline ulong uboot_cntr_val(void)
  87. {
  88. return readl(CNTMR_VAL_REG(UBOOT_CNTR));
  89. }
  90. void __udelay(unsigned long usec)
  91. {
  92. uint current;
  93. ulong delayticks;
  94. current = uboot_cntr_val();
  95. delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
  96. if (current < delayticks) {
  97. delayticks -= current;
  98. while (uboot_cntr_val() < current)
  99. ;
  100. while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
  101. ;
  102. } else {
  103. while (uboot_cntr_val() > (current - delayticks))
  104. ;
  105. }
  106. }
  107. /*
  108. * init the counter
  109. */
  110. int timer_init(void)
  111. {
  112. unsigned int cntmrctrl;
  113. /* load value into timer */
  114. writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
  115. writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
  116. /* enable timer in auto reload mode */
  117. cntmrctrl = readl(CNTMR_CTRL_REG);
  118. cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
  119. cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
  120. writel(cntmrctrl, CNTMR_CTRL_REG);
  121. return 0;
  122. }
  123. void timer_init_r(void)
  124. {
  125. /* init the timestamp and lastdec value */
  126. lastdec = read_timer();
  127. timestamp = 0;
  128. }
  129. /*
  130. * This function is derived from PowerPC code (read timebase as long long).
  131. * On ARM it just returns the timer value.
  132. */
  133. unsigned long long get_ticks(void)
  134. {
  135. return get_timer(0);
  136. }
  137. /*
  138. * This function is derived from PowerPC code (timebase clock frequency).
  139. * On ARM it returns the number of timer ticks per second.
  140. */
  141. ulong get_tbclk (void)
  142. {
  143. return (ulong)CONFIG_SYS_HZ;
  144. }