lowlevel_init.S 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * (C) Copyright 2009
  6. * Marvell Semiconductor <www.marvell.com>
  7. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  8. */
  9. #include <config.h>
  10. #include "asm/arch/orion5x.h"
  11. /*
  12. * Configuration values for SDRAM access setup
  13. */
  14. #define SDRAM_CONFIG 0x3148400
  15. #define SDRAM_MODE 0x62
  16. #define SDRAM_CONTROL 0x4041000
  17. #define SDRAM_TIME_CTRL_LOW 0x11602220
  18. #define SDRAM_TIME_CTRL_HI 0x40c
  19. #define SDRAM_OPEN_PAGE_EN 0x0
  20. /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
  21. #define SDRAM_BANK0_SIZE 0x3ff0001
  22. #define SDRAM_ADDR_CTRL 0x10
  23. #define SDRAM_OP_NOP 0x05
  24. #define SDRAM_OP_SETMODE 0x03
  25. #define SDRAM_PAD_CTRL_WR_EN 0x80000000
  26. #define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
  27. #define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
  28. #define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
  29. /*
  30. * For Guideline MEM-3 - Drive Strength value
  31. */
  32. #define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
  33. #define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
  34. /*
  35. * For Guideline MEM-4 - DQS Reference Delay Tuning
  36. */
  37. #define MSAR_ARMDDRCLCK_MASK 0x000000f0
  38. #define MSAR_ARMDDRCLCK_H_MASK 0x00000100
  39. #define MSAR_ARMDDRCLCK_333_167 0x00000000
  40. #define MSAR_ARMDDRCLCK_500_167 0x00000030
  41. #define MSAR_ARMDDRCLCK_667_167 0x00000060
  42. #define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
  43. #define MSAR_ARMDDRCLCK_400_200 0x00000010
  44. #define MSAR_ARMDDRCLCK_600_200 0x00000050
  45. #define MSAR_ARMDDRCLCK_800_200 0x00000070
  46. #define FTDLL_DDR1_166MHZ 0x0047F001
  47. #define FTDLL_DDR1_200MHZ 0x0044D001
  48. /*
  49. * Low-level init happens right after start.S has switched to SVC32,
  50. * flushed and disabled caches and disabled MMU. We're still running
  51. * from the boot chip select, so the first thing SPL should do is to
  52. * set up the RAM to copy U-Boot into.
  53. */
  54. .globl lowlevel_init
  55. lowlevel_init:
  56. #ifdef CONFIG_SPL_BUILD
  57. /* Use 'r2 as the base for internal register accesses */
  58. ldr r2, =ORION5X_REGS_PHY_BASE
  59. /* move internal registers from the default 0xD0000000
  60. * to their intended location, defined by SoC */
  61. ldr r3, =0xD0000000
  62. add r3, r3, #0x20000
  63. str r2, [r3, #0x80]
  64. /* Use R3 as the base for DRAM registers */
  65. add r3, r2, #0x01000
  66. /*DDR SDRAM Initialization Control */
  67. ldr r0, =0x00000001
  68. str r0, [r3, #0x480]
  69. /* Use R3 as the base for PCI registers */
  70. add r3, r2, #0x31000
  71. /* Disable arbiter */
  72. ldr r0, =0x00000030
  73. str r0, [r3, #0xd00]
  74. /* Use R3 as the base for DRAM registers */
  75. add r3, r2, #0x01000
  76. /* set all dram windows to 0 */
  77. mov r0, #0
  78. str r0, [r3, #0x504]
  79. str r0, [r3, #0x50C]
  80. str r0, [r3, #0x514]
  81. str r0, [r3, #0x51C]
  82. /* 1) Configure SDRAM */
  83. ldr r0, =SDRAM_CONFIG
  84. str r0, [r3, #0x400]
  85. /* 2) Set SDRAM Control reg */
  86. ldr r0, =SDRAM_CONTROL
  87. str r0, [r3, #0x404]
  88. /* 3) Write SDRAM address control register */
  89. ldr r0, =SDRAM_ADDR_CTRL
  90. str r0, [r3, #0x410]
  91. /* 4) Write SDRAM bank 0 size register */
  92. ldr r0, =SDRAM_BANK0_SIZE
  93. str r0, [r3, #0x504]
  94. /* keep other banks disabled */
  95. /* 5) Write SDRAM open pages control register */
  96. ldr r0, =SDRAM_OPEN_PAGE_EN
  97. str r0, [r3, #0x414]
  98. /* 6) Write SDRAM timing Low register */
  99. ldr r0, =SDRAM_TIME_CTRL_LOW
  100. str r0, [r3, #0x408]
  101. /* 7) Write SDRAM timing High register */
  102. ldr r0, =SDRAM_TIME_CTRL_HI
  103. str r0, [r3, #0x40C]
  104. /* 8) Write SDRAM mode register */
  105. /* The CPU must not attempt to change the SDRAM Mode register setting */
  106. /* prior to DRAM controller completion of the DRAM initialization */
  107. /* sequence. To guarantee this restriction, it is recommended that */
  108. /* the CPU sets the SDRAM Operation register to NOP command, performs */
  109. /* read polling until the register is back in Normal operation value, */
  110. /* and then sets SDRAM Mode register to its new value. */
  111. /* 8.1 write 'nop' to SDRAM operation */
  112. ldr r0, =SDRAM_OP_NOP
  113. str r0, [r3, #0x418]
  114. /* 8.2 poll SDRAM operation until back in 'normal' mode. */
  115. 1:
  116. ldr r0, [r3, #0x418]
  117. cmp r0, #0
  118. bne 1b
  119. /* 8.3 Now its safe to write new value to SDRAM Mode register */
  120. ldr r0, =SDRAM_MODE
  121. str r0, [r3, #0x41C]
  122. /* 8.4 Set new mode */
  123. ldr r0, =SDRAM_OP_SETMODE
  124. str r0, [r3, #0x418]
  125. /* 8.5 poll SDRAM operation until back in 'normal' mode. */
  126. 2:
  127. ldr r0, [r3, #0x418]
  128. cmp r0, #0
  129. bne 2b
  130. /* DDR SDRAM Address/Control Pads Calibration */
  131. ldr r0, [r3, #0x4C0]
  132. /* Set Bit [31] to make the register writable */
  133. orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
  134. str r0, [r3, #0x4C0]
  135. bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
  136. bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
  137. bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
  138. bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
  139. /* Get the final N locked value of driving strength [22:17] */
  140. mov r1, r0
  141. mov r1, r1, LSL #9
  142. mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
  143. orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
  144. /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
  145. orr r0, r0, r1
  146. str r0, [r3, #0x4C0]
  147. /* DDR SDRAM Data Pads Calibration */
  148. ldr r0, [r3, #0x4C4]
  149. /* Set Bit [31] to make the register writable */
  150. orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
  151. str r0, [r3, #0x4C4]
  152. bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
  153. bic r0, r0, #SDRAM_PAD_CTRL_TUNE_EN
  154. bic r0, r0, #SDRAM_PAD_CTRL_DRVN_MASK
  155. bic r0, r0, #SDRAM_PAD_CTRL_DRVP_MASK
  156. /* Get the final N locked value of driving strength [22:17] */
  157. mov r1, r0
  158. mov r1, r1, LSL #9
  159. mov r1, r1, LSR #26
  160. orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
  161. /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
  162. orr r0, r0, r1
  163. str r0, [r3, #0x4C4]
  164. /* Implement Guideline (GL# MEM-3) Drive Strength Value */
  165. /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
  166. ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
  167. /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
  168. ldr r0, [r3, #0x4C0]
  169. orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
  170. str r0, [r3, #0x4C0]
  171. /* Correct strength and disable writes again */
  172. bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
  173. bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
  174. orr r0, r0, r1
  175. str r0, [r3, #0x4C0]
  176. /* Enable writes to DDR SDRAM Data Pads Calibration register */
  177. ldr r0, [r3, #0x4C4]
  178. orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
  179. str r0, [r3, #0x4C4]
  180. /* Correct strength and disable writes again */
  181. bic r0, r0, #SDRAM_PAD_CTRL_DRV_STR_MASK
  182. bic r0, r0, #SDRAM_PAD_CTRL_WR_EN
  183. orr r0, r0, r1
  184. str r0, [r3, #0x4C4]
  185. /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
  186. /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
  187. /* Get the "sample on reset" register for the DDR frequancy */
  188. ldr r3, =0x10000
  189. ldr r0, [r3, #0x010]
  190. ldr r1, =MSAR_ARMDDRCLCK_MASK
  191. and r1, r0, r1
  192. ldr r0, =FTDLL_DDR1_166MHZ
  193. cmp r1, #MSAR_ARMDDRCLCK_333_167
  194. beq 3f
  195. cmp r1, #MSAR_ARMDDRCLCK_500_167
  196. beq 3f
  197. cmp r1, #MSAR_ARMDDRCLCK_667_167
  198. beq 3f
  199. ldr r0, =FTDLL_DDR1_200MHZ
  200. cmp r1, #MSAR_ARMDDRCLCK_400_200_1
  201. beq 3f
  202. cmp r1, #MSAR_ARMDDRCLCK_400_200
  203. beq 3f
  204. cmp r1, #MSAR_ARMDDRCLCK_600_200
  205. beq 3f
  206. cmp r1, #MSAR_ARMDDRCLCK_800_200
  207. beq 3f
  208. ldr r0, =0
  209. 3:
  210. /* Use R3 as the base for DRAM registers */
  211. add r3, r2, #0x01000
  212. ldr r2, [r3, #0x484]
  213. orr r2, r2, r0
  214. str r2, [r3, #0x484]
  215. /* enable for 2 GB DDR; detection should find out real amount */
  216. sub r0, r0, r0
  217. str r0, [r3, #0x500]
  218. ldr r0, =0x7fff0001
  219. str r0, [r3, #0x504]
  220. #endif /* CONFIG_SPL_BUILD */
  221. /* Return to U-Boot via saved link register */
  222. mov pc, lr