dram.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * (C) Copyright 2009
  7. * Marvell Semiconductor <www.marvell.com>
  8. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  9. */
  10. #include <common.h>
  11. #include <config.h>
  12. #include <asm/arch/cpu.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /*
  15. * orion5x_sdram_bar - reads SDRAM Base Address Register
  16. */
  17. u32 orion5x_sdram_bar(enum memory_bank bank)
  18. {
  19. struct orion5x_ddr_addr_decode_registers *winregs =
  20. (struct orion5x_ddr_addr_decode_registers *)
  21. ORION5X_DRAM_BASE;
  22. u32 result = 0;
  23. u32 enable = 0x01 & winregs[bank].size;
  24. if ((!enable) || (bank > BANK3))
  25. return 0;
  26. result = winregs[bank].base;
  27. return result;
  28. }
  29. int dram_init (void)
  30. {
  31. /* dram_init must store complete ramsize in gd->ram_size */
  32. gd->ram_size = get_ram_size(
  33. (long *) orion5x_sdram_bar(0),
  34. CONFIG_MAX_RAM_BANK_SIZE);
  35. return 0;
  36. }
  37. int dram_init_banksize(void)
  38. {
  39. int i;
  40. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  41. gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
  42. gd->bd->bi_dram[i].size = get_ram_size(
  43. (long *) (gd->bd->bi_dram[i].start),
  44. CONFIG_MAX_RAM_BANK_SIZE);
  45. }
  46. return 0;
  47. }