pipe3-phy.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI PIPE3 PHY
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <sata.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <linux/errno.h>
  14. #include "pipe3-phy.h"
  15. /* PLLCTRL Registers */
  16. #define PLL_STATUS 0x00000004
  17. #define PLL_GO 0x00000008
  18. #define PLL_CONFIGURATION1 0x0000000C
  19. #define PLL_CONFIGURATION2 0x00000010
  20. #define PLL_CONFIGURATION3 0x00000014
  21. #define PLL_CONFIGURATION4 0x00000020
  22. #define PLL_REGM_MASK 0x001FFE00
  23. #define PLL_REGM_SHIFT 9
  24. #define PLL_REGM_F_MASK 0x0003FFFF
  25. #define PLL_REGM_F_SHIFT 0
  26. #define PLL_REGN_MASK 0x000001FE
  27. #define PLL_REGN_SHIFT 1
  28. #define PLL_SELFREQDCO_MASK 0x0000000E
  29. #define PLL_SELFREQDCO_SHIFT 1
  30. #define PLL_SD_MASK 0x0003FC00
  31. #define PLL_SD_SHIFT 10
  32. #define SET_PLL_GO 0x1
  33. #define PLL_TICOPWDN BIT(16)
  34. #define PLL_LDOPWDN BIT(15)
  35. #define PLL_LOCK 0x2
  36. #define PLL_IDLE 0x1
  37. /* PHY POWER CONTROL Register */
  38. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
  39. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
  40. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
  41. #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
  42. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
  43. #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
  44. #define PLL_IDLE_TIME 100 /* in milliseconds */
  45. #define PLL_LOCK_TIME 100 /* in milliseconds */
  46. static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
  47. {
  48. return __raw_readl(addr + offset);
  49. }
  50. static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
  51. u32 data)
  52. {
  53. __raw_writel(data, addr + offset);
  54. }
  55. static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
  56. *pipe3)
  57. {
  58. u32 rate;
  59. struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
  60. rate = get_sys_clk_freq();
  61. for (; dpll_map->rate; dpll_map++) {
  62. if (rate == dpll_map->rate)
  63. return &dpll_map->params;
  64. }
  65. printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
  66. __func__, rate);
  67. return NULL;
  68. }
  69. static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
  70. {
  71. u32 val;
  72. int timeout = PLL_LOCK_TIME;
  73. do {
  74. mdelay(1);
  75. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  76. if (val & PLL_LOCK)
  77. break;
  78. } while (--timeout);
  79. if (!(val & PLL_LOCK)) {
  80. printf("%s: DPLL failed to lock\n", __func__);
  81. return -EBUSY;
  82. }
  83. return 0;
  84. }
  85. static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
  86. {
  87. u32 val;
  88. struct pipe3_dpll_params *dpll_params;
  89. dpll_params = omap_pipe3_get_dpll_params(phy);
  90. if (!dpll_params) {
  91. printf("%s: Invalid DPLL parameters\n", __func__);
  92. return -EINVAL;
  93. }
  94. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  95. val &= ~PLL_REGN_MASK;
  96. val |= dpll_params->n << PLL_REGN_SHIFT;
  97. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  98. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  99. val &= ~PLL_SELFREQDCO_MASK;
  100. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  101. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  102. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  103. val &= ~PLL_REGM_MASK;
  104. val |= dpll_params->m << PLL_REGM_SHIFT;
  105. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  106. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
  107. val &= ~PLL_REGM_F_MASK;
  108. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  109. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
  110. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
  111. val &= ~PLL_SD_MASK;
  112. val |= dpll_params->sd << PLL_SD_SHIFT;
  113. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
  114. omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  115. return omap_pipe3_wait_lock(phy);
  116. }
  117. static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
  118. {
  119. u32 val, rate;
  120. val = readl(phy->power_reg);
  121. rate = get_sys_clk_freq();
  122. rate = rate/1000000;
  123. if (on) {
  124. val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  125. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  126. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
  127. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  128. val |= rate <<
  129. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  130. } else {
  131. val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  132. val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
  133. OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
  134. }
  135. writel(val, phy->power_reg);
  136. }
  137. int phy_pipe3_power_on(struct omap_pipe3 *phy)
  138. {
  139. int ret;
  140. u32 val;
  141. /* Program the DPLL only if not locked */
  142. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  143. if (!(val & PLL_LOCK)) {
  144. ret = omap_pipe3_dpll_program(phy);
  145. if (ret)
  146. return ret;
  147. } else {
  148. /* else just bring it out of IDLE mode */
  149. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  150. if (val & PLL_IDLE) {
  151. val &= ~PLL_IDLE;
  152. omap_pipe3_writel(phy->pll_ctrl_base,
  153. PLL_CONFIGURATION2, val);
  154. ret = omap_pipe3_wait_lock(phy);
  155. if (ret)
  156. return ret;
  157. }
  158. }
  159. /* Power up the PHY */
  160. omap_control_phy_power(phy, 1);
  161. return 0;
  162. }
  163. int phy_pipe3_power_off(struct omap_pipe3 *phy)
  164. {
  165. u32 val;
  166. int timeout = PLL_IDLE_TIME;
  167. /* Power down the PHY */
  168. omap_control_phy_power(phy, 0);
  169. /* Put DPLL in IDLE mode */
  170. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  171. val |= PLL_IDLE;
  172. omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  173. /* wait for LDO and Oscillator to power down */
  174. do {
  175. mdelay(1);
  176. val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  177. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  178. break;
  179. } while (--timeout);
  180. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  181. printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
  182. __func__, val);
  183. return -EBUSY;
  184. }
  185. return 0;
  186. }