clocks-common.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Clock initialization for OMAP4
  5. *
  6. * (C) Copyright 2010
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Aneesh V <aneesh@ti.com>
  10. *
  11. * Based on previous work by:
  12. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  13. * Rajendra Nayak <rnayak@ti.com>
  14. */
  15. #include <common.h>
  16. #include <i2c.h>
  17. #include <asm/omap_common.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/utils.h>
  22. #include <asm/omap_gpio.h>
  23. #include <asm/emif.h>
  24. #ifndef CONFIG_SPL_BUILD
  25. /*
  26. * printing to console doesn't work unless
  27. * this code is executed from SPL
  28. */
  29. #define printf(fmt, args...)
  30. #define puts(s)
  31. #endif
  32. const u32 sys_clk_array[8] = {
  33. 12000000, /* 12 MHz */
  34. 20000000, /* 20 MHz */
  35. 16800000, /* 16.8 MHz */
  36. 19200000, /* 19.2 MHz */
  37. 26000000, /* 26 MHz */
  38. 27000000, /* 27 MHz */
  39. 38400000, /* 38.4 MHz */
  40. };
  41. static inline u32 __get_sys_clk_index(void)
  42. {
  43. s8 ind;
  44. /*
  45. * For ES1 the ROM code calibration of sys clock is not reliable
  46. * due to hw issue. So, use hard-coded value. If this value is not
  47. * correct for any board over-ride this function in board file
  48. * From ES2.0 onwards you will get this information from
  49. * CM_SYS_CLKSEL
  50. */
  51. if (omap_revision() == OMAP4430_ES1_0)
  52. ind = OMAP_SYS_CLK_IND_38_4_MHZ;
  53. else {
  54. /* SYS_CLKSEL - 1 to match the dpll param array indices */
  55. ind = (readl((*prcm)->cm_sys_clksel) &
  56. CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
  57. }
  58. return ind;
  59. }
  60. u32 get_sys_clk_index(void)
  61. __attribute__ ((weak, alias("__get_sys_clk_index")));
  62. u32 get_sys_clk_freq(void)
  63. {
  64. u8 index = get_sys_clk_index();
  65. return sys_clk_array[index];
  66. }
  67. void setup_post_dividers(u32 const base, const struct dpll_params *params)
  68. {
  69. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  70. /* Setup post-dividers */
  71. if (params->m2 >= 0)
  72. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  73. if (params->m3 >= 0)
  74. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  75. if (params->m4_h11 >= 0)
  76. writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
  77. if (params->m5_h12 >= 0)
  78. writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
  79. if (params->m6_h13 >= 0)
  80. writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
  81. if (params->m7_h14 >= 0)
  82. writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
  83. if (params->h21 >= 0)
  84. writel(params->h21, &dpll_regs->cm_div_h21_dpll);
  85. if (params->h22 >= 0)
  86. writel(params->h22, &dpll_regs->cm_div_h22_dpll);
  87. if (params->h23 >= 0)
  88. writel(params->h23, &dpll_regs->cm_div_h23_dpll);
  89. if (params->h24 >= 0)
  90. writel(params->h24, &dpll_regs->cm_div_h24_dpll);
  91. }
  92. static inline void do_bypass_dpll(u32 const base)
  93. {
  94. struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
  95. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  96. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  97. DPLL_EN_FAST_RELOCK_BYPASS <<
  98. CM_CLKMODE_DPLL_EN_SHIFT);
  99. }
  100. static inline void wait_for_bypass(u32 const base)
  101. {
  102. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  103. if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
  104. LDELAY)) {
  105. printf("Bypassing DPLL failed %x\n", base);
  106. }
  107. }
  108. static inline void do_lock_dpll(u32 const base)
  109. {
  110. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  111. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  112. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  113. DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
  114. }
  115. static inline void wait_for_lock(u32 const base)
  116. {
  117. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  118. if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
  119. &dpll_regs->cm_idlest_dpll, LDELAY)) {
  120. printf("DPLL locking failed for %x\n", base);
  121. hang();
  122. }
  123. }
  124. inline u32 check_for_lock(u32 const base)
  125. {
  126. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  127. u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
  128. return lock;
  129. }
  130. const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
  131. {
  132. u32 sysclk_ind = get_sys_clk_index();
  133. return &dpll_data->mpu[sysclk_ind];
  134. }
  135. const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
  136. {
  137. u32 sysclk_ind = get_sys_clk_index();
  138. return &dpll_data->core[sysclk_ind];
  139. }
  140. const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
  141. {
  142. u32 sysclk_ind = get_sys_clk_index();
  143. return &dpll_data->per[sysclk_ind];
  144. }
  145. const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
  146. {
  147. u32 sysclk_ind = get_sys_clk_index();
  148. return &dpll_data->iva[sysclk_ind];
  149. }
  150. const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
  151. {
  152. u32 sysclk_ind = get_sys_clk_index();
  153. return &dpll_data->usb[sysclk_ind];
  154. }
  155. const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
  156. {
  157. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  158. u32 sysclk_ind = get_sys_clk_index();
  159. return &dpll_data->abe[sysclk_ind];
  160. #else
  161. return dpll_data->abe;
  162. #endif
  163. }
  164. static const struct dpll_params *get_ddr_dpll_params
  165. (struct dplls const *dpll_data)
  166. {
  167. u32 sysclk_ind = get_sys_clk_index();
  168. if (!dpll_data->ddr)
  169. return NULL;
  170. return &dpll_data->ddr[sysclk_ind];
  171. }
  172. #ifdef CONFIG_DRIVER_TI_CPSW
  173. static const struct dpll_params *get_gmac_dpll_params
  174. (struct dplls const *dpll_data)
  175. {
  176. u32 sysclk_ind = get_sys_clk_index();
  177. if (!dpll_data->gmac)
  178. return NULL;
  179. return &dpll_data->gmac[sysclk_ind];
  180. }
  181. #endif
  182. static void do_setup_dpll(u32 const base, const struct dpll_params *params,
  183. u8 lock, char *dpll)
  184. {
  185. u32 temp, M, N;
  186. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  187. if (!params)
  188. return;
  189. temp = readl(&dpll_regs->cm_clksel_dpll);
  190. if (check_for_lock(base)) {
  191. /*
  192. * The Dpll has already been locked by rom code using CH.
  193. * Check if M,N are matching with Ideal nominal opp values.
  194. * If matches, skip the rest otherwise relock.
  195. */
  196. M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
  197. N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
  198. if ((M != (params->m)) || (N != (params->n))) {
  199. debug("\n %s Dpll locked, but not for ideal M = %d,"
  200. "N = %d values, current values are M = %d,"
  201. "N= %d" , dpll, params->m, params->n,
  202. M, N);
  203. } else {
  204. /* Dpll locked with ideal values for nominal opps. */
  205. debug("\n %s Dpll already locked with ideal"
  206. "nominal opp values", dpll);
  207. bypass_dpll(base);
  208. goto setup_post_dividers;
  209. }
  210. }
  211. bypass_dpll(base);
  212. /* Set M & N */
  213. temp &= ~CM_CLKSEL_DPLL_M_MASK;
  214. temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
  215. temp &= ~CM_CLKSEL_DPLL_N_MASK;
  216. temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
  217. writel(temp, &dpll_regs->cm_clksel_dpll);
  218. setup_post_dividers:
  219. setup_post_dividers(base, params);
  220. /* Lock */
  221. if (lock)
  222. do_lock_dpll(base);
  223. /* Wait till the DPLL locks */
  224. if (lock)
  225. wait_for_lock(base);
  226. }
  227. u32 omap_ddr_clk(void)
  228. {
  229. u32 ddr_clk, sys_clk_khz, omap_rev, divider;
  230. const struct dpll_params *core_dpll_params;
  231. omap_rev = omap_revision();
  232. sys_clk_khz = get_sys_clk_freq() / 1000;
  233. core_dpll_params = get_core_dpll_params(*dplls_data);
  234. debug("sys_clk %d\n ", sys_clk_khz * 1000);
  235. /* Find Core DPLL locked frequency first */
  236. ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
  237. (core_dpll_params->n + 1);
  238. if (omap_rev < OMAP5430_ES1_0) {
  239. /*
  240. * DDR frequency is PHY_ROOT_CLK/2
  241. * PHY_ROOT_CLK = Fdpll/2/M2
  242. */
  243. divider = 4;
  244. } else {
  245. /*
  246. * DDR frequency is PHY_ROOT_CLK
  247. * PHY_ROOT_CLK = Fdpll/2/M2
  248. */
  249. divider = 2;
  250. }
  251. ddr_clk = ddr_clk / divider / core_dpll_params->m2;
  252. ddr_clk *= 1000; /* convert to Hz */
  253. debug("ddr_clk %d\n ", ddr_clk);
  254. return ddr_clk;
  255. }
  256. /*
  257. * Lock MPU dpll
  258. *
  259. * Resulting MPU frequencies:
  260. * 4430 ES1.0 : 600 MHz
  261. * 4430 ES2.x : 792 MHz (OPP Turbo)
  262. * 4460 : 920 MHz (OPP Turbo) - DCC disabled
  263. */
  264. void configure_mpu_dpll(void)
  265. {
  266. const struct dpll_params *params;
  267. struct dpll_regs *mpu_dpll_regs;
  268. u32 omap_rev;
  269. omap_rev = omap_revision();
  270. /*
  271. * DCC and clock divider settings for 4460.
  272. * DCC is required, if more than a certain frequency is required.
  273. * For, 4460 > 1GHZ.
  274. * 5430 > 1.4GHZ.
  275. */
  276. if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
  277. mpu_dpll_regs =
  278. (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
  279. bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
  280. clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  281. MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
  282. setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  283. MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
  284. clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
  285. CM_CLKSEL_DCC_EN_MASK);
  286. }
  287. params = get_mpu_dpll_params(*dplls_data);
  288. do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
  289. debug("MPU DPLL locked\n");
  290. }
  291. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  292. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  293. static void setup_usb_dpll(void)
  294. {
  295. const struct dpll_params *params;
  296. u32 sys_clk_khz, sd_div, num, den;
  297. sys_clk_khz = get_sys_clk_freq() / 1000;
  298. /*
  299. * USB:
  300. * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
  301. * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
  302. * - where CLKINP is sys_clk in MHz
  303. * Use CLKINP in KHz and adjust the denominator accordingly so
  304. * that we have enough accuracy and at the same time no overflow
  305. */
  306. params = get_usb_dpll_params(*dplls_data);
  307. num = params->m * sys_clk_khz;
  308. den = (params->n + 1) * 250 * 1000;
  309. num += den - 1;
  310. sd_div = num / den;
  311. clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
  312. CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
  313. sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
  314. /* Now setup the dpll with the regular function */
  315. do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
  316. }
  317. #endif
  318. static void setup_dplls(void)
  319. {
  320. u32 temp;
  321. const struct dpll_params *params;
  322. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  323. debug("setup_dplls\n");
  324. /* CORE dpll */
  325. params = get_core_dpll_params(*dplls_data); /* default - safest */
  326. /*
  327. * Do not lock the core DPLL now. Just set it up.
  328. * Core DPLL will be locked after setting up EMIF
  329. * using the FREQ_UPDATE method(freq_update_core())
  330. */
  331. if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
  332. EMIF_SDRAM_TYPE_LPDDR2)
  333. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  334. DPLL_NO_LOCK, "core");
  335. else
  336. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  337. DPLL_LOCK, "core");
  338. /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
  339. temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
  340. (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
  341. (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
  342. writel(temp, (*prcm)->cm_clksel_core);
  343. debug("Core DPLL configured\n");
  344. /* lock PER dpll */
  345. params = get_per_dpll_params(*dplls_data);
  346. do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
  347. params, DPLL_LOCK, "per");
  348. debug("PER DPLL locked\n");
  349. /* MPU dpll */
  350. configure_mpu_dpll();
  351. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  352. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  353. setup_usb_dpll();
  354. #endif
  355. params = get_ddr_dpll_params(*dplls_data);
  356. do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
  357. params, DPLL_LOCK, "ddr");
  358. #ifdef CONFIG_DRIVER_TI_CPSW
  359. params = get_gmac_dpll_params(*dplls_data);
  360. do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
  361. DPLL_LOCK, "gmac");
  362. #endif
  363. }
  364. u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
  365. {
  366. u32 offset_code;
  367. volt_offset -= pmic->base_offset;
  368. offset_code = (volt_offset + pmic->step - 1) / pmic->step;
  369. /*
  370. * Offset codes 1-6 all give the base voltage in Palmas
  371. * Offset code 0 switches OFF the SMPS
  372. */
  373. return offset_code + pmic->start_code;
  374. }
  375. void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  376. {
  377. u32 offset_code;
  378. u32 offset = volt_mv;
  379. int ret = 0;
  380. if (!volt_mv)
  381. return;
  382. pmic->pmic_bus_init();
  383. /* See if we can first get the GPIO if needed */
  384. if (pmic->gpio_en)
  385. ret = gpio_request(pmic->gpio, "PMIC_GPIO");
  386. if (ret < 0) {
  387. printf("%s: gpio %d request failed %d\n", __func__,
  388. pmic->gpio, ret);
  389. return;
  390. }
  391. /* Pull the GPIO low to select SET0 register, while we program SET1 */
  392. if (pmic->gpio_en)
  393. gpio_direction_output(pmic->gpio, 0);
  394. /* convert to uV for better accuracy in the calculations */
  395. offset *= 1000;
  396. offset_code = get_offset_code(offset, pmic);
  397. debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
  398. offset_code);
  399. if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
  400. printf("Scaling voltage failed for 0x%x\n", vcore_reg);
  401. if (pmic->gpio_en)
  402. gpio_direction_output(pmic->gpio, 1);
  403. }
  404. int __weak get_voltrail_opp(int rail_offset)
  405. {
  406. /*
  407. * By default return OPP_NOM for all voltage rails.
  408. */
  409. return OPP_NOM;
  410. }
  411. static u32 optimize_vcore_voltage(struct volts const *v, int opp)
  412. {
  413. u32 val;
  414. if (!v->value[opp])
  415. return 0;
  416. if (!v->efuse.reg[opp])
  417. return v->value[opp];
  418. switch (v->efuse.reg_bits) {
  419. case 16:
  420. val = readw(v->efuse.reg[opp]);
  421. break;
  422. case 32:
  423. val = readl(v->efuse.reg[opp]);
  424. break;
  425. default:
  426. printf("Error: efuse 0x%08x bits=%d unknown\n",
  427. v->efuse.reg[opp], v->efuse.reg_bits);
  428. return v->value[opp];
  429. }
  430. if (!val) {
  431. printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
  432. v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
  433. return v->value[opp];
  434. }
  435. debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
  436. __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
  437. val);
  438. return val;
  439. }
  440. #ifdef CONFIG_IODELAY_RECALIBRATION
  441. void __weak recalibrate_iodelay(void)
  442. {
  443. }
  444. #endif
  445. /*
  446. * Setup the voltages for the main SoC core power domains.
  447. * We start with the maximum voltages allowed here, as set in the corresponding
  448. * vcores_data struct, and then scale (usually down) to the fused values that
  449. * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
  450. * are initialised.
  451. * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
  452. * compiled conditionally. Note that the new code writes the scaled (or zeroed)
  453. * values back to the vcores_data struct for eventual reuse. Zero values mean
  454. * that the corresponding rails are not controlled separately, and are not sent
  455. * to the PMIC.
  456. */
  457. void scale_vcores(struct vcores_data const *vcores)
  458. {
  459. int i, opp, j, ol;
  460. struct volts *pv = (struct volts *)vcores;
  461. struct volts *px;
  462. for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
  463. opp = get_voltrail_opp(i);
  464. debug("%d -> ", pv->value[opp]);
  465. if (pv->value[opp]) {
  466. /* Handle non-empty members only */
  467. pv->value[opp] = optimize_vcore_voltage(pv, opp);
  468. px = (struct volts *)vcores;
  469. j = 0;
  470. while (px < pv) {
  471. /*
  472. * Scan already handled non-empty members to see
  473. * if we have a group and find the max voltage,
  474. * which is set to the first occurance of the
  475. * particular SMPS; the other group voltages are
  476. * zeroed.
  477. */
  478. ol = get_voltrail_opp(j);
  479. if (px->value[ol] &&
  480. (pv->pmic->i2c_slave_addr ==
  481. px->pmic->i2c_slave_addr) &&
  482. (pv->addr == px->addr)) {
  483. /* Same PMIC, same SMPS */
  484. if (pv->value[opp] > px->value[ol])
  485. px->value[ol] = pv->value[opp];
  486. pv->value[opp] = 0;
  487. }
  488. px++;
  489. j++;
  490. }
  491. }
  492. debug("%d\n", pv->value[opp]);
  493. pv++;
  494. }
  495. opp = get_voltrail_opp(VOLT_CORE);
  496. debug("cor: %d\n", vcores->core.value[opp]);
  497. do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
  498. vcores->core.pmic);
  499. /*
  500. * IO delay recalibration should be done immediately after
  501. * adjusting AVS voltages for VDD_CORE_L.
  502. * Respective boards should call __recalibrate_iodelay()
  503. * with proper mux, virtual and manual mode configurations.
  504. */
  505. #ifdef CONFIG_IODELAY_RECALIBRATION
  506. recalibrate_iodelay();
  507. #endif
  508. opp = get_voltrail_opp(VOLT_MPU);
  509. debug("mpu: %d\n", vcores->mpu.value[opp]);
  510. do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
  511. vcores->mpu.pmic);
  512. /* Configure MPU ABB LDO after scale */
  513. abb_setup(vcores->mpu.efuse.reg[opp],
  514. (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
  515. (*prcm)->prm_abbldo_mpu_setup,
  516. (*prcm)->prm_abbldo_mpu_ctrl,
  517. (*prcm)->prm_irqstatus_mpu_2,
  518. vcores->mpu.abb_tx_done_mask,
  519. OMAP_ABB_FAST_OPP);
  520. opp = get_voltrail_opp(VOLT_MM);
  521. debug("mm: %d\n", vcores->mm.value[opp]);
  522. do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
  523. vcores->mm.pmic);
  524. /* Configure MM ABB LDO after scale */
  525. abb_setup(vcores->mm.efuse.reg[opp],
  526. (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
  527. (*prcm)->prm_abbldo_mm_setup,
  528. (*prcm)->prm_abbldo_mm_ctrl,
  529. (*prcm)->prm_irqstatus_mpu,
  530. vcores->mm.abb_tx_done_mask,
  531. OMAP_ABB_FAST_OPP);
  532. opp = get_voltrail_opp(VOLT_GPU);
  533. debug("gpu: %d\n", vcores->gpu.value[opp]);
  534. do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
  535. vcores->gpu.pmic);
  536. /* Configure GPU ABB LDO after scale */
  537. abb_setup(vcores->gpu.efuse.reg[opp],
  538. (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
  539. (*prcm)->prm_abbldo_gpu_setup,
  540. (*prcm)->prm_abbldo_gpu_ctrl,
  541. (*prcm)->prm_irqstatus_mpu,
  542. vcores->gpu.abb_tx_done_mask,
  543. OMAP_ABB_FAST_OPP);
  544. opp = get_voltrail_opp(VOLT_EVE);
  545. debug("eve: %d\n", vcores->eve.value[opp]);
  546. do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
  547. vcores->eve.pmic);
  548. /* Configure EVE ABB LDO after scale */
  549. abb_setup(vcores->eve.efuse.reg[opp],
  550. (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
  551. (*prcm)->prm_abbldo_eve_setup,
  552. (*prcm)->prm_abbldo_eve_ctrl,
  553. (*prcm)->prm_irqstatus_mpu,
  554. vcores->eve.abb_tx_done_mask,
  555. OMAP_ABB_FAST_OPP);
  556. opp = get_voltrail_opp(VOLT_IVA);
  557. debug("iva: %d\n", vcores->iva.value[opp]);
  558. do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
  559. vcores->iva.pmic);
  560. /* Configure IVA ABB LDO after scale */
  561. abb_setup(vcores->iva.efuse.reg[opp],
  562. (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
  563. (*prcm)->prm_abbldo_iva_setup,
  564. (*prcm)->prm_abbldo_iva_ctrl,
  565. (*prcm)->prm_irqstatus_mpu,
  566. vcores->iva.abb_tx_done_mask,
  567. OMAP_ABB_FAST_OPP);
  568. }
  569. static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
  570. {
  571. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  572. enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
  573. debug("Enable clock domain - %x\n", clkctrl_reg);
  574. }
  575. static inline void disable_clock_domain(u32 const clkctrl_reg)
  576. {
  577. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  578. CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
  579. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  580. debug("Disable clock domain - %x\n", clkctrl_reg);
  581. }
  582. static inline void wait_for_clk_enable(u32 clkctrl_addr)
  583. {
  584. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  585. u32 bound = LDELAY;
  586. while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  587. (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  588. clkctrl = readl(clkctrl_addr);
  589. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  590. MODULE_CLKCTRL_IDLEST_SHIFT;
  591. if (--bound == 0) {
  592. printf("Clock enable failed for 0x%x idlest 0x%x\n",
  593. clkctrl_addr, clkctrl);
  594. return;
  595. }
  596. }
  597. }
  598. static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
  599. u32 wait_for_enable)
  600. {
  601. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  602. enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
  603. debug("Enable clock module - %x\n", clkctrl_addr);
  604. if (wait_for_enable)
  605. wait_for_clk_enable(clkctrl_addr);
  606. }
  607. static inline void wait_for_clk_disable(u32 clkctrl_addr)
  608. {
  609. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
  610. u32 bound = LDELAY;
  611. while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
  612. clkctrl = readl(clkctrl_addr);
  613. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  614. MODULE_CLKCTRL_IDLEST_SHIFT;
  615. if (--bound == 0) {
  616. printf("Clock disable failed for 0x%x idlest 0x%x\n",
  617. clkctrl_addr, clkctrl);
  618. return;
  619. }
  620. }
  621. }
  622. static inline void disable_clock_module(u32 const clkctrl_addr,
  623. u32 wait_for_disable)
  624. {
  625. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  626. MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
  627. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  628. debug("Disable clock module - %x\n", clkctrl_addr);
  629. if (wait_for_disable)
  630. wait_for_clk_disable(clkctrl_addr);
  631. }
  632. void freq_update_core(void)
  633. {
  634. u32 freq_config1 = 0;
  635. const struct dpll_params *core_dpll_params;
  636. u32 omap_rev = omap_revision();
  637. core_dpll_params = get_core_dpll_params(*dplls_data);
  638. /* Put EMIF clock domain in sw wakeup mode */
  639. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  640. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  641. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  642. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  643. freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
  644. SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
  645. freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
  646. SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
  647. freq_config1 |= (core_dpll_params->m2 <<
  648. SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
  649. SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
  650. writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
  651. if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
  652. (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
  653. puts("FREQ UPDATE procedure failed!!");
  654. hang();
  655. }
  656. /*
  657. * Putting EMIF in HW_AUTO is seen to be causing issues with
  658. * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
  659. * in OMAP5430 ES1.0 silicon
  660. */
  661. if (omap_rev != OMAP5430_ES1_0) {
  662. /* Put EMIF clock domain back in hw auto mode */
  663. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  664. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  665. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  666. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  667. }
  668. }
  669. void bypass_dpll(u32 const base)
  670. {
  671. do_bypass_dpll(base);
  672. wait_for_bypass(base);
  673. }
  674. void lock_dpll(u32 const base)
  675. {
  676. do_lock_dpll(base);
  677. wait_for_lock(base);
  678. }
  679. static void setup_clocks_for_console(void)
  680. {
  681. /* Do not add any spl_debug prints in this function */
  682. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  683. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  684. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  685. /* Enable all UARTs - console will be on one of them */
  686. clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
  687. MODULE_CLKCTRL_MODULEMODE_MASK,
  688. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  689. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  690. clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
  691. MODULE_CLKCTRL_MODULEMODE_MASK,
  692. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  693. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  694. clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
  695. MODULE_CLKCTRL_MODULEMODE_MASK,
  696. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  697. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  698. clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
  699. MODULE_CLKCTRL_MODULEMODE_MASK,
  700. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  701. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  702. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  703. CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
  704. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  705. }
  706. void do_enable_clocks(u32 const *clk_domains,
  707. u32 const *clk_modules_hw_auto,
  708. u32 const *clk_modules_explicit_en,
  709. u8 wait_for_enable)
  710. {
  711. u32 i, max = 100;
  712. /* Put the clock domains in SW_WKUP mode */
  713. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  714. enable_clock_domain(clk_domains[i],
  715. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  716. }
  717. /* Clock modules that need to be put in HW_AUTO */
  718. for (i = 0; (i < max) && clk_modules_hw_auto &&
  719. clk_modules_hw_auto[i]; i++) {
  720. enable_clock_module(clk_modules_hw_auto[i],
  721. MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
  722. wait_for_enable);
  723. };
  724. /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
  725. for (i = 0; (i < max) && clk_modules_explicit_en &&
  726. clk_modules_explicit_en[i]; i++) {
  727. enable_clock_module(clk_modules_explicit_en[i],
  728. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
  729. wait_for_enable);
  730. };
  731. /* Put the clock domains in HW_AUTO mode now */
  732. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  733. enable_clock_domain(clk_domains[i],
  734. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  735. }
  736. }
  737. void do_disable_clocks(u32 const *clk_domains,
  738. u32 const *clk_modules_disable,
  739. u8 wait_for_disable)
  740. {
  741. u32 i, max = 100;
  742. /* Clock modules that need to be put in SW_DISABLE */
  743. for (i = 0; (i < max) && clk_modules_disable[i]; i++)
  744. disable_clock_module(clk_modules_disable[i],
  745. wait_for_disable);
  746. /* Put the clock domains in SW_SLEEP mode */
  747. for (i = 0; (i < max) && clk_domains[i]; i++)
  748. disable_clock_domain(clk_domains[i]);
  749. }
  750. /**
  751. * setup_early_clocks() - Setup early clocks needed for SoC
  752. *
  753. * Setup clocks for console, SPL basic initialization clocks and initialize
  754. * the timer. This is invoked prior prcm_init.
  755. */
  756. void setup_early_clocks(void)
  757. {
  758. switch (omap_hw_init_context()) {
  759. case OMAP_INIT_CONTEXT_SPL:
  760. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  761. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  762. setup_clocks_for_console();
  763. enable_basic_clocks();
  764. timer_init();
  765. /* Fall through */
  766. }
  767. }
  768. void prcm_init(void)
  769. {
  770. switch (omap_hw_init_context()) {
  771. case OMAP_INIT_CONTEXT_SPL:
  772. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  773. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  774. scale_vcores(*omap_vcores);
  775. setup_dplls();
  776. setup_warmreset_time();
  777. break;
  778. default:
  779. break;
  780. }
  781. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
  782. enable_basic_uboot_clocks();
  783. }
  784. #if !defined(CONFIG_DM_I2C)
  785. void gpi2c_init(void)
  786. {
  787. static int gpi2c = 1;
  788. if (gpi2c) {
  789. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  790. CONFIG_SYS_OMAP24_I2C_SLAVE);
  791. gpi2c = 0;
  792. }
  793. }
  794. #endif