mpddrc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. *
  6. * Copyright (C) 2015 Atmel Corporation
  7. * Wenyou Yang <wenyou.yang@atmel.com>
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/atmel_mpddrc.h>
  12. #include <asm/arch/at91_common.h>
  13. #define SAMA5D3_MPDDRC_VERSION 0x140
  14. static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
  15. int mode,
  16. u32 ram_address)
  17. {
  18. writel(mode, &mpddr->mr);
  19. dmb();
  20. writel(0, ram_address);
  21. }
  22. static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
  23. {
  24. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  25. u16 version = readl(&mpddr->version) & 0xffff;
  26. if ((version >= SAMA5D3_MPDDRC_VERSION) &&
  27. (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
  28. return 0;
  29. return 1;
  30. }
  31. int ddr2_init(const unsigned int base,
  32. const unsigned int ram_address,
  33. const struct atmel_mpddrc_config *mpddr_value)
  34. {
  35. const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  36. u32 ba_off, cr;
  37. /* Compute bank offset according to NC in configuration register */
  38. ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
  39. if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
  40. ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
  41. ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
  42. /* Program the memory device type into the memory device register */
  43. writel(mpddr_value->md, &mpddr->md);
  44. /* Program the configuration register */
  45. writel(mpddr_value->cr, &mpddr->cr);
  46. /* Program the timing register */
  47. writel(mpddr_value->tpr0, &mpddr->tpr0);
  48. writel(mpddr_value->tpr1, &mpddr->tpr1);
  49. writel(mpddr_value->tpr2, &mpddr->tpr2);
  50. /* Issue a NOP command */
  51. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  52. /* A 200 us is provided to precede any signal toggle */
  53. udelay(200);
  54. /* Issue a NOP command */
  55. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  56. /* Issue an all banks precharge command */
  57. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  58. /* Issue an extended mode register set(EMRS2) to choose operation */
  59. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  60. ram_address + (0x2 << ba_off));
  61. /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
  62. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  63. ram_address + (0x3 << ba_off));
  64. /*
  65. * Issue an extended mode register set(EMRS1) to enable DLL and
  66. * program D.I.C (output driver impedance control)
  67. */
  68. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  69. ram_address + (0x1 << ba_off));
  70. /* Enable DLL reset */
  71. cr = readl(&mpddr->cr);
  72. writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
  73. /* A mode register set(MRS) cycle is issued to reset DLL */
  74. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  75. /* Issue an all banks precharge command */
  76. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  77. /* Two auto-refresh (CBR) cycles are provided */
  78. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  79. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  80. /* Disable DLL reset */
  81. cr = readl(&mpddr->cr);
  82. writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
  83. /* A mode register set (MRS) cycle is issued to disable DLL reset */
  84. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  85. /* Set OCD calibration in default state */
  86. cr = readl(&mpddr->cr);
  87. writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
  88. /*
  89. * An extended mode register set (EMRS1) cycle is issued
  90. * to OCD default value
  91. */
  92. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  93. ram_address + (0x1 << ba_off));
  94. /* OCD calibration mode exit */
  95. cr = readl(&mpddr->cr);
  96. writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
  97. /*
  98. * An extended mode register set (EMRS1) cycle is issued
  99. * to enable OCD exit
  100. */
  101. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  102. ram_address + (0x1 << ba_off));
  103. /* A nornal mode command is provided */
  104. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  105. /* Perform a write access to any DDR2-SDRAM address */
  106. writel(0, ram_address);
  107. /* Write the refresh rate */
  108. writel(mpddr_value->rtr, &mpddr->rtr);
  109. return 0;
  110. }
  111. int ddr3_init(const unsigned int base,
  112. const unsigned int ram_address,
  113. const struct atmel_mpddrc_config *mpddr_value)
  114. {
  115. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  116. u32 ba_off;
  117. /* Compute bank offset according to NC in configuration register */
  118. ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
  119. if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
  120. ba_off += ((mpddr_value->cr &
  121. ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
  122. ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
  123. /* Program the memory device type */
  124. writel(mpddr_value->md, &mpddr->md);
  125. /*
  126. * Program features of the DDR3-SDRAM device and timing parameters
  127. */
  128. writel(mpddr_value->cr, &mpddr->cr);
  129. writel(mpddr_value->tpr0, &mpddr->tpr0);
  130. writel(mpddr_value->tpr1, &mpddr->tpr1);
  131. writel(mpddr_value->tpr2, &mpddr->tpr2);
  132. /* A NOP command is issued to the DDR3-SRAM */
  133. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  134. /* A pause of at least 500us must be observed before a single toggle. */
  135. udelay(500);
  136. /* A NOP command is issued to the DDR3-SDRAM */
  137. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  138. /*
  139. * An Extended Mode Register Set (EMRS2) cycle is issued to choose
  140. * between commercial or high temperature operations.
  141. */
  142. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  143. ram_address + (0x2 << ba_off));
  144. /*
  145. * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
  146. * the Extended Mode Register to 0.
  147. */
  148. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  149. ram_address + (0x3 << ba_off));
  150. /*
  151. * An Extended Mode Register Set (EMRS1) cycle is issued to disable and
  152. * to program O.D.S. (Output Driver Strength).
  153. */
  154. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  155. ram_address + (0x1 << ba_off));
  156. /*
  157. * Write a one to the DLL bit (enable DLL reset) in the MPDDRC
  158. * Configuration Register.
  159. */
  160. /* A Mode Register Set (MRS) cycle is issued to reset DLL. */
  161. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  162. udelay(50);
  163. /*
  164. * A Calibration command (MRS) is issued to calibrate RTT and RON
  165. * values for the Process Voltage Temperature (PVT).
  166. */
  167. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
  168. /* A Normal Mode command is provided. */
  169. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  170. /* Perform a write access to any DDR3-SDRAM address. */
  171. writel(0, ram_address);
  172. /*
  173. * Write the refresh rate into the COUNT field in the MPDDRC
  174. * Refresh Timer Register (MPDDRC_RTR):
  175. */
  176. writel(mpddr_value->rtr, &mpddr->rtr);
  177. return 0;
  178. }
  179. int lpddr2_init(const unsigned int base,
  180. const unsigned int ram_address,
  181. const struct atmel_mpddrc_config *mpddr_value)
  182. {
  183. struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  184. u32 reg;
  185. writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr);
  186. writel(mpddr_value->tim_cal, &mpddr->tim_cal);
  187. /* 1. Program the memory device type */
  188. writel(mpddr_value->md, &mpddr->md);
  189. /*
  190. * 2. Program features of the LPDDR2-SDRAM device and timing parameters
  191. */
  192. writel(mpddr_value->cr, &mpddr->cr);
  193. writel(mpddr_value->tpr0, &mpddr->tpr0);
  194. writel(mpddr_value->tpr1, &mpddr->tpr1);
  195. writel(mpddr_value->tpr2, &mpddr->tpr2);
  196. /* 3. A NOP command is issued to the LPDDR2-SDRAM */
  197. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  198. /*
  199. * 3bis. Add memory barrier then Perform a write access to
  200. * any low-power DDR2-SDRAM address to acknowledge the command.
  201. */
  202. dmb();
  203. writel(0, ram_address);
  204. /* 4. A pause of at least 100 ns must be observed before a single toggle */
  205. udelay(1);
  206. /* 5. A NOP command is issued to the LPDDR2-SDRAM */
  207. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  208. /* 6. A pause of at least 200 us must be observed before a Reset Command */
  209. udelay(200);
  210. /* 7. A Reset command is issued to the low-power DDR2-SDRAM. */
  211. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  212. ATMEL_MPDDRC_MR_MRS(63), ram_address);
  213. /*
  214. * 8. A pause of at least tINIT5 must be observed before issuing
  215. * any commands
  216. */
  217. udelay(1);
  218. /* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */
  219. reg = readl(&mpddr->cr);
  220. reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
  221. reg |= ATMEL_MPDDRC_CR_ZQ_RESET;
  222. writel(reg, &mpddr->cr);
  223. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  224. ATMEL_MPDDRC_MR_MRS(10), ram_address);
  225. /*
  226. * 9bis: The ZQ Calibration command is now issued.
  227. * Program the type of calibration in the MPDDRC_CR: set the
  228. * ZQ field to the SHORT value.
  229. */
  230. reg = readl(&mpddr->cr);
  231. reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
  232. reg |= ATMEL_MPDDRC_CR_ZQ_SHORT;
  233. writel(reg, &mpddr->cr);
  234. /*
  235. * 10: A Mode Register Write command with 1 to the MRS field
  236. * is issued to the low-power DDR2-SDRAM.
  237. */
  238. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  239. ATMEL_MPDDRC_MR_MRS(1), ram_address);
  240. /*
  241. * 11: A Mode Register Write command with 2 to the MRS field
  242. * is issued to the low-power DDR2-SDRAM.
  243. */
  244. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  245. ATMEL_MPDDRC_MR_MRS(2), ram_address);
  246. /*
  247. * 12: A Mode Register Write command with 3 to the MRS field
  248. * is issued to the low-power DDR2-SDRAM.
  249. */
  250. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  251. ATMEL_MPDDRC_MR_MRS(3), ram_address);
  252. /*
  253. * 13: A Mode Register Write command with 16 to the MRS field
  254. * is issued to the low-power DDR2-SDRAM.
  255. */
  256. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  257. ATMEL_MPDDRC_MR_MRS(16), ram_address);
  258. /*
  259. * 14: In the DDR Configuration Register, open the input buffers.
  260. */
  261. #ifdef CONFIG_ATMEL_SFR
  262. configure_ddrcfg_input_buffers(true);
  263. #endif
  264. /* 15. A NOP command is issued to the LPDDR2-SDRAM */
  265. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  266. /*
  267. * 16: A Mode Register Write command with 5 to the MRS field
  268. * is issued to the low-power DDR2-SDRAM.
  269. */
  270. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  271. ATMEL_MPDDRC_MR_MRS(5), ram_address);
  272. /*
  273. * 17: A Mode Register Write command with 6 to the MRS field
  274. * is issued to the low-power DDR2-SDRAM.
  275. */
  276. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  277. ATMEL_MPDDRC_MR_MRS(6), ram_address);
  278. /*
  279. * 18: A Mode Register Write command with 8 to the MRS field
  280. * is issued to the low-power DDR2-SDRAM.
  281. */
  282. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  283. ATMEL_MPDDRC_MR_MRS(8), ram_address);
  284. /*
  285. * 19: A Mode Register Write command with 0 to the MRS field
  286. * is issued to the low-power DDR2-SDRAM.
  287. */
  288. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
  289. ATMEL_MPDDRC_MR_MRS(0), ram_address);
  290. /*
  291. * 20: A Normal Mode command is provided.
  292. */
  293. atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  294. /* 21: In the DDR Configuration Register, close the input buffers. */
  295. #ifdef CONFIG_ATMEL_SFR
  296. configure_ddrcfg_input_buffers(false);
  297. #endif
  298. /*
  299. * 22: Write the refresh rate into the COUNT field in the MPDDRC
  300. * Refresh Timer Register.
  301. */
  302. writel(mpddr_value->rtr, &mpddr->rtr);
  303. /* 23. Configre CAL MR4 register */
  304. writel(mpddr_value->cal_mr4, &mpddr->cal_mr4);
  305. return 0;
  306. }