asm-offsets.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
  4. *
  5. * This program is used to generate definitions needed by
  6. * assembly language modules.
  7. *
  8. * We use the technique used in the OSF Mach kernel code:
  9. * generate asm statements containing #defines,
  10. * compile this file to assembler, and then extract the
  11. * #defines from the assembly-language output.
  12. */
  13. #include <common.h>
  14. #include <linux/kbuild.h>
  15. #include <linux/arm-smccc.h>
  16. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
  17. || defined(CONFIG_MX51) || defined(CONFIG_MX53)
  18. #include <asm/arch/imx-regs.h>
  19. #endif
  20. int main(void)
  21. {
  22. /*
  23. * TODO : Check if each entry in this file is really necessary.
  24. * - struct esdramc_regs
  25. * - struct max_regs
  26. * - struct aips_regs
  27. * - struct aipi_regs
  28. * - struct clkctl
  29. * - struct dpll
  30. * are used only for generating asm-offsets.h.
  31. * It means their offset addresses are referenced only from assembly
  32. * code. Is it better to define the macros directly in headers?
  33. */
  34. #if defined(CONFIG_MX25)
  35. /* Clock Control Module */
  36. DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
  37. DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
  38. DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
  39. DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
  40. DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
  41. DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
  42. /* Enhanced SDRAM Controller */
  43. DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
  44. DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
  45. DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
  46. /* Multi-Layer AHB Crossbar Switch */
  47. DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
  48. DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
  49. DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
  50. DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
  51. DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
  52. DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
  53. DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
  54. DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
  55. DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
  56. DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
  57. DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
  58. DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
  59. DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
  60. DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
  61. DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
  62. /* AHB <-> IP-Bus Interface */
  63. DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
  64. DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
  65. #endif
  66. #if defined(CONFIG_MX27)
  67. DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
  68. DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
  69. DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
  70. DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
  71. DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
  72. DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
  73. DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
  74. DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
  75. DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
  76. DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
  77. DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
  78. DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
  79. DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
  80. DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
  81. DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
  82. DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
  83. DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
  84. offsetof(struct system_control_regs, gpcr));
  85. DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
  86. offsetof(struct system_control_regs, fmcr));
  87. #endif
  88. #if defined(CONFIG_MX35)
  89. /* Round up to make sure size gives nice stack alignment */
  90. DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
  91. DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
  92. DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
  93. DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
  94. DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
  95. DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
  96. DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
  97. DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
  98. DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
  99. DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
  100. DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
  101. DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
  102. DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
  103. DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
  104. DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
  105. /* Multi-Layer AHB Crossbar Switch */
  106. DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
  107. DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
  108. DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
  109. DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
  110. DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
  111. DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
  112. DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
  113. DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
  114. DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
  115. DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
  116. DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
  117. DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
  118. DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
  119. DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
  120. DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
  121. DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
  122. /* AHB <-> IP-Bus Interface */
  123. DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
  124. DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
  125. DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
  126. DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
  127. DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
  128. DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
  129. DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
  130. DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
  131. DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
  132. DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
  133. DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
  134. #endif
  135. #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  136. /* Round up to make sure size gives nice stack alignment */
  137. DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
  138. DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
  139. DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
  140. DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
  141. DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
  142. DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
  143. DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
  144. DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
  145. DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
  146. DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
  147. DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
  148. DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
  149. DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
  150. DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
  151. DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
  152. DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
  153. DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
  154. DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
  155. DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
  156. DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
  157. DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
  158. DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
  159. DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
  160. DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
  161. DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
  162. DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
  163. DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
  164. DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
  165. DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
  166. DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
  167. DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
  168. DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
  169. DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
  170. DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
  171. #if defined(CONFIG_MX53)
  172. DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
  173. #endif
  174. /* DPLL */
  175. DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
  176. DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
  177. DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
  178. DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
  179. DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
  180. DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
  181. DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
  182. DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
  183. #endif
  184. #ifdef CONFIG_ARM_SMCCC
  185. DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
  186. DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
  187. DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
  188. DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
  189. #endif
  190. return 0;
  191. }