sys_clk.h 4.6 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file sys_clk.h
  6. * @brief header file for setting system frequency.
  7. * @version V1.0
  8. * @date 9. April 2020
  9. ******************************************************************************/
  10. #ifndef _SYS_CLK_H_
  11. #define _SYS_CLK_H_
  12. #include <stdint.h>
  13. #ifdef SEC_LIB_VERSION
  14. #include "drv/common.h"
  15. #else
  16. #include "common.h"
  17. #endif
  18. #ifdef __cplusplus
  19. extern "C" {
  20. #endif
  21. typedef enum {
  22. IHS_CLK = 0U, /* internal high speed clock */
  23. EHS_CLK, /* external high speed clock */
  24. ILS_CLK, /* internal low speed clock */
  25. ELS_CLK, /* external low speed clock */
  26. PLL_CLK /* PLL clock */
  27. } clk_src_t;
  28. typedef enum {
  29. CPU_300MHZ = 300000000U,
  30. CPU_288MHZ = 288000000U,
  31. CPU_276MHZ = 276000000U,
  32. CPU_270MHZ = 270000000U,
  33. CPU_264MHZ = 264000000U,
  34. CPU_252MHZ = 252000000U,
  35. CPU_245_76MHZ = 245760000U,
  36. CPU_240MHZ = 240000000U,
  37. CPU_228MHZ = 228000000U,
  38. CPU_216MHZ = 216000000U,
  39. CPU_204MHZ = 204000000U,
  40. CPU_192MHZ = 192000000U,
  41. CPU_180MHZ = 180000000U,
  42. CPU_168MHZ = 168000000U,
  43. CPU_156MHZ = 156000000U,
  44. CPU_144MHZ = 144000000U,
  45. CPU_135MHZ = 135000000U,
  46. CPU_132MHZ = 132000000U,
  47. CPU_120MHZ = 120000000U,
  48. CPU_108MHZ = 108000000U,
  49. CPU_96MHZ = 96000000U,
  50. CPU_84MHZ = 84000000U,
  51. CPU_72MHZ = 72000000U,
  52. CPU_60MHZ = 60000000U,
  53. CPU_48MHZ = 48000000U,
  54. CPU_36MHZ = 36000000U,
  55. CPU_30MHZ = 30000000U,
  56. CPU_24MHZ = 24000000U,
  57. CPU_20MHZ = 20000000U,
  58. CPU_10MHZ = 10000000U,
  59. } sys_freq_t;
  60. /* pllclkout : ( pllclkin / 2)*( FN + Frac/4096 ) */
  61. typedef struct {
  62. uint32_t pll_is_used; /* pll is used */
  63. uint32_t pll_source; /* select pll input source clock */
  64. uint32_t pll_src_clk_divider; /* ratio between pll_srcclk clock and pll_clkin clock */
  65. uint32_t fn; /* integer value of frequency division */
  66. uint32_t frac; /* decimal value of frequency division */
  67. } pll_config_t;
  68. typedef struct {
  69. uint32_t system_clk; /* system clock */
  70. // pll_config_t pll_config; /* pll config struct */
  71. uint32_t sys_clk_source; /* select sysclk source clock */
  72. uint32_t rtc_clk_source; /* select rtcclk source clock */
  73. uint32_t cpu_clk_divider; /* ratio between fs_mclk clock and mclk clock */
  74. uint32_t sys_clk_divider; /* ratio between fs_mclk clock and mclk clock */
  75. uint32_t ahb_clk_divider; /* ratio between mclk clock and ahb clock */
  76. uint32_t apb_clk_divider; /* ratio between mclk clock and apb clock */
  77. uint32_t uart_clk_divider; /* ratio between mclk clock and uart clock */
  78. uint32_t audio_clk_divider; /* ratio between mclk clock and audio clock */
  79. uint32_t vad_clk_divider; /* ratio between mclk clock and vad clock */
  80. } system_clk_config_t;
  81. typedef enum {
  82. CLK_DIV1 = 0U,
  83. CLK_DIV2,
  84. CLK_DIV3,
  85. CLK_DIV4,
  86. CLK_DIV5,
  87. CLK_DIV6,
  88. CLK_DIV7,
  89. CLK_DIV8,
  90. CLK_DIV9,
  91. CLK_DIV10,
  92. CLK_DIV11,
  93. CLK_DIV12,
  94. CLK_DIV13,
  95. CLK_DIV14,
  96. CLK_DIV15,
  97. CLK_DIV16
  98. } apb_div_t;
  99. typedef enum {
  100. PLL_FN_18 = 0U,
  101. PLL_FN_19,
  102. PLL_FN_20,
  103. PLL_FN_21,
  104. PLL_FN_22,
  105. PLL_FN_23,
  106. PLL_FN_24,
  107. PLL_FN_25,
  108. PLL_FN_26,
  109. PLL_FN_27,
  110. PLL_FN_28,
  111. PLL_FN_29,
  112. PLL_FN_30,
  113. PLL_FN_31,
  114. PLL_FN_32,
  115. PLL_FN_33,
  116. PLL_FN_34,
  117. PLL_FN_35,
  118. PLL_FN_36,
  119. PLL_FN_37,
  120. PLL_FN_38,
  121. PLL_FN_39,
  122. PLL_FN_40,
  123. PLL_FN_41,
  124. PLL_FN_42,
  125. PLL_FN_43,
  126. PLL_FN_44,
  127. PLL_FN_45,
  128. PLL_FN_46,
  129. PLL_FN_47,
  130. PLL_FN_48,
  131. PLL_FN_49
  132. } pll_fn_t;
  133. typedef enum {
  134. TIM0_CLK = 0U,
  135. TIM1_CLK,
  136. RTC0_CLK,
  137. WDT_CLK,
  138. SPI0_CLK,
  139. UART0_CLK,
  140. IIC0_CLK,
  141. PWM_CLK,
  142. QSPI0_CLK,
  143. PWMR_CLK,
  144. EFUSE_CLK,
  145. I2S0_CLK,
  146. I2S1_CLK,
  147. GPIO0_CLK,
  148. TIM2_CLK = 32U,
  149. TIM3_CLK,
  150. SPI1_CLK,
  151. UART1_CLK,
  152. I2S567_CLK,
  153. ADC_CLK,
  154. ETB_CLK,
  155. I2S2_CLK,
  156. I2S3_CLK,
  157. IOC_CLK,
  158. CODEC_CLK
  159. } clk_module_t;
  160. /**
  161. \brief Set the system clock according to the parameter
  162. \param[in] config system clock config.
  163. \return error code
  164. */
  165. csi_error_t soc_sysclk_config(system_clk_config_t *config);
  166. /**
  167. \brief Set iic reset
  168. \param[in] idx iic idx.
  169. \return Null
  170. */
  171. void soc_reset_iic(uint32_t idx);
  172. #ifdef __cplusplus
  173. }
  174. #endif
  175. #endif /* _SYS_CLK_H_ */