soc.h 14 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file soc.h
  6. * @brief CSI Core Peripheral Access Layer Header File for
  7. * CSKYSOC Device Series
  8. * @version V1.0
  9. * @date 7. April 2020
  10. ******************************************************************************/
  11. #ifndef _SOC_H_
  12. #define _SOC_H_
  13. #include <stdint.h>
  14. #include "csi_core.h"
  15. #include "sys_clk.h"
  16. #ifdef __cplusplus
  17. extern "C" {
  18. #endif
  19. #ifndef EHS_VALUE
  20. #define EHS_VALUE 20000000U
  21. #endif
  22. #ifndef ELS_VALUE
  23. #define ELS_VALUE 32768U
  24. #endif
  25. #ifndef IHS_VALUE
  26. #define IHS_VALUE 50000000U
  27. #endif
  28. #ifndef ILS_VALUE
  29. #define ILS_VALUE 32768U
  30. #endif
  31. #define RISCV_CORE_TIM_FREQ 3000000
  32. typedef enum {
  33. Supervisor_Software_IRQn = 1U,
  34. Machine_Software_IRQn = 3U,
  35. Supervisor_Timer_IRQn = 5U,
  36. CORET_IRQn = 7U,
  37. Supervisor_External_IRQn = 9U,
  38. Machine_External_IRQn = 11U,
  39. DW_TIMER0_IRQn = 16U,
  40. DW_TIMER1_IRQn = 17U,
  41. DW_TIMER2_IRQn = 18U,
  42. DW_TIMER3_IRQn = 19U,
  43. DW_TIMER4_IRQn = 20U,
  44. DW_TIMER5_IRQn = 21U,
  45. DW_TIMER6_IRQn = 22U,
  46. DW_TIMER7_IRQn = 23U,
  47. WJ_MBOX_IRQn = 28U,
  48. DW_UART0_IRQn = 36U,
  49. DW_UART1_IRQn = 37U,
  50. DW_UART2_IRQn = 38U,
  51. DW_UART3_IRQn = 39U,
  52. DW_UART4_IRQn = 40U,
  53. DW_UART5_IRQn = 41U,
  54. DW_I2C0_IRQn = 44U,
  55. DW_I2C2_IRQn = 46U,
  56. DW_QSPI0_IRQn = 52U,
  57. DW_QSPI1_IRQn = 53U,
  58. DW_SPI0_IRQn = 54U,
  59. DW_GPIO0_IRQn = 56U,
  60. DW_GPIO1_IRQn = 57U,
  61. DW_GPIO2_IRQn = 58U,
  62. DW_GPIO3_IRQn = 59U,
  63. DW_EMMC_IRQn = 62U,
  64. DW_SD_IRQn = 64U,
  65. DW_USB_IRQn = 68U,
  66. DW_DMA0_IRQn = 27U,
  67. DCD_ISO7816_IRQn = 69U,
  68. DW_DMA1_IRQn = 71U,
  69. DW_DMA2_IRQn = 72U,
  70. DW_DMA3_IRQn = 73U,
  71. WJ_EFUSE_IRQn = 80U,
  72. DW_WDT0_IRQn = 111U,
  73. DW_WDT1_IRQn = 112U,
  74. RB_120SI_AV_IRQn = 121U,
  75. RB_120SII_AV_IRQn = 124U,
  76. RB_120SIII_AV_IRQn = 127U,
  77. RB_150B_AIC_IRQn = 128U,
  78. RB_150B_PKA1_IRQn = 130U,
  79. RB_150B_ERR_IRQn = 132U,
  80. RB_150B_TRNG_IRQn = 133U,
  81. } irqn_type_t;
  82. typedef enum {
  83. WJ_IOCTL_Wakeupn = 29U, /* IOCTOL wakeup */
  84. } wakeupn_type_t;
  85. typedef enum {
  86. WJ_USB_CLK_MANAGERN = 28U,
  87. } clk_manager_type_t;
  88. typedef enum {
  89. PAD_GRP_BASE1,
  90. PAD_UART0_TXD = PAD_GRP_BASE1,
  91. PAD_UART0_RXD,
  92. PAD_QSPI0_SCLK,
  93. PAD_QSPI0_CSN0,
  94. PAD_QSPI0_CSN1,
  95. PAD_QSPI0_D0_MOSI,
  96. PAD_QSPI0_D1_MISO,
  97. PAD_QSPI0_D2_WP,
  98. PAD_QSPI0_D3_HOLD,
  99. PAD_I2C2_SCL,
  100. PAD_I2C2_SDA,
  101. PAD_I2C3_SCL,
  102. PAD_I2C3_SDA,
  103. PAD_GPIO2_13,
  104. PAD_SPI_SCLK,
  105. PAD_SPI_CSN,
  106. PAD_SPI_MOSI,
  107. PAD_SPI_MISO,
  108. PAD_GPIO2_18,
  109. PAD_GPIO2_19,
  110. PAD_GPIO2_20,
  111. PAD_GPIO2_21,
  112. PAD_GPIO2_22,
  113. PAD_GPIO2_23,
  114. PAD_GPIO2_24,
  115. PAD_GPIO2_25,
  116. PAD_SDIO0_WPRTN,
  117. PAD_SDIO0_DETN,
  118. PAD_SDIO1_WPRTN,
  119. PAD_SDIO1_DETN,
  120. PAD_GPIO2_30,
  121. PAD_GPIO2_31,
  122. PAD_GPIO3_0,
  123. PAD_GPIO3_1,
  124. PAD_GPIO3_2,
  125. PAD_GPIO3_3,
  126. PAD_HDMI_SCL,
  127. PAD_HDMI_SDA,
  128. PAD_HDMI_CEC,
  129. PAD_GMAC0_TX_CLK,
  130. PAD_GMAC0_RX_CLK,
  131. PAD_GMAC0_TXEN,
  132. PAD_GMAC0_TXD0,
  133. PAD_GMAC0_TXD1,
  134. PAD_GMAC0_TXD2,
  135. PAD_GMAC0_TXD3,
  136. PAD_GMAC0_RXDV,
  137. PAD_GMAC0_RXD0,
  138. PAD_GMAC0_RXD1,
  139. PAD_GMAC0_RXD2,
  140. PAD_GMAC0_RXD3,
  141. PAD_GMAC0_MDC,
  142. PAD_GMAC0_MDIO,
  143. PAD_GMAC0_COL,
  144. PAD_GMAC0_CRS,
  145. PAD_GRP_BASE2,
  146. PAD_QSPI1_SCLK = PAD_GRP_BASE2,
  147. PAD_QSPI1_CSN0,
  148. PAD_QSPI1_D0_MOSI,
  149. PAD_QSPI1_D1_MISO,
  150. PAD_QSPI1_D2_WP,
  151. PAD_QSPI1_D3_HOLD,
  152. PAD_I2C0_SCL,
  153. PAD_I2C0_SDA,
  154. PAD_I2C1_SCL,
  155. PAD_I2C1_SDA,
  156. PAD_UART1_TXD,
  157. PAD_UART1_RXD,
  158. PAD_UART4_TXD,
  159. PAD_UART4_RXD,
  160. PAD_UART4_CTSN,
  161. PAD_UART4_RTSN,
  162. PAD_UART3_TXD,
  163. PAD_UART3_RXD,
  164. PAD_GPIO0_18,
  165. PAD_GPIO0_19,
  166. PAD_GPIO0_20,
  167. PAD_GPIO0_21,
  168. PAD_GPIO0_22,
  169. PAD_GPIO0_23,
  170. PAD_GPIO0_24,
  171. PAD_GPIO0_25,
  172. PAD_GPIO0_26,
  173. PAD_GPIO0_27,
  174. PAD_GPIO0_28,
  175. PAD_GPIO0_29,
  176. PAD_GPIO0_30,
  177. PAD_GPIO0_31,
  178. PAD_GPIO1_0,
  179. PAD_GPIO1_1,
  180. PAD_GPIO1_2,
  181. PAD_GPIO1_3,
  182. PAD_GPIO1_4,
  183. PAD_GPIO1_5,
  184. PAD_GPIO1_6,
  185. PAD_GPIO1_7,
  186. PAD_GPIO1_8,
  187. PAD_GPIO1_9,
  188. PAD_GPIO1_10,
  189. PAD_GPIO1_11,
  190. PAD_GPIO1_12,
  191. PAD_GPIO1_13,
  192. PAD_GPIO1_14,
  193. PAD_GPIO1_15,
  194. PAD_GPIO1_16,
  195. PAD_CLK_OUT_0,
  196. PAD_CLK_OUT_1,
  197. PAD_CLK_OUT_2,
  198. PAD_CLK_OUT_3,
  199. PAD_GPIO1_21,
  200. PAD_GPIO1_22,
  201. PAD_GPIO1_23,
  202. PAD_GPIO1_24,
  203. PAD_GPIO1_25,
  204. PAD_GPIO1_26,
  205. PAD_GPIO1_27,
  206. PAD_GPIO1_28,
  207. PAD_GPIO1_29,
  208. PAD_GPIO1_30,
  209. } pin_name_t;
  210. typedef enum {
  211. PAD_UART0_TXD_ALT_TXD =0,
  212. PAD_UART0_TXD_ALT_GPIO2_0 =3,
  213. PAD_UART0_RXD_ALT_RXD =0,
  214. PAD_UART0_RXD_ALT_GPIO2_1 =3,
  215. PAD_QSPI0_SCLK_ALT_QSPI0_SCK= 0,
  216. PAD_QSPI0_SCLK_ALT_PWM0 = 1,
  217. PAD_QSPI0_SCLK_ALT_I2S_SDA0 = 2,
  218. PAD_QSPI0_SCLK_ALT_GPIO2_2 = 3,
  219. PAD_QSPI0_CSN0_ALT_QSPI0_CSN0=0,
  220. PAD_QSPI0_CSN0_ALT_PWM1 =1,
  221. PAD_QSPI0_CSN0_ALT_I2S_SDA1 =2,
  222. PAD_QSPI0_CSN0_ALT_GPIO2_3 =3,
  223. PAD_QSPI0_CSN1_ALT_QSPI0_CSN1=0,
  224. PAD_QSPI0_CSN1_ALT_PWM2 =1,
  225. PAD_QSPI0_CSN1_ALT_I2S_SDA2 =2,
  226. PAD_QSPI0_CSN1_ALT_GPIO2_4 =3,
  227. PAD_QSPI0_D0_MOSI_ALT_QSPI0_MOSI=0,
  228. PAD_QSPI0_D0_MOSI_ALT_PWM3 =1,
  229. PAD_QSPI0_D0_MOSI_ALT_I2S_SDA3 =2,
  230. PAD_QSPI0_D0_MOSI_ALT_GPIO2_5 =3,
  231. PAD_QSPI0_D1_MISO_ALT_QSPI0_MISO=0,
  232. PAD_QSPI0_D1_MISO_ALT_QSPI0_PWM4=1,
  233. PAD_QSPI0_D1_MISO_ALT_I2S_MCLK =2,
  234. PAD_QSPI0_D1_MISO_ALT_GPIO2_6 =3,
  235. PAD_QSPI0_D2_WP_ALT_QSPI0_WP =0,
  236. PAD_QSPI0_D2_WP_ALT_PWM5 =1,
  237. PAD_QSPI0_D2_WP_ALT_I2S_SCK =2,
  238. PAD_QSPI0_D2_WP_ALT_GIOP2_7 =3,
  239. PAD_QSPI0_D3_HOLD_ALT_QSPI0_HOLD=0,
  240. PAD_QSPI0_D3_HOLD_ALT_I2S_WS =2,
  241. PAD_QSPI0_D3_HOLD_ALT_GPIO2_8 =3,
  242. PAD_UART1_TXD_ALT_TXD =0,
  243. PAD_UART1_TXD_ALT_GPIO0_10 =3,
  244. PAD_UART1_RXD_ALT_RXD =0,
  245. PAD_UART1_RXD_ALT_GPIO011 =3,
  246. PIN_FUNC_GPIO = 3U,
  247. } pin_func_t;
  248. #define CONFIG_GPIO_NUM 3
  249. #define CONFIG_IRQ_NUM 112
  250. #define CONFIG_DMA_NUM 1
  251. #define WJ_EFUSE_BASE 0xFFFF210000UL
  252. #define WJ_EFUSE_SIZE 0x10000U
  253. #define DW_USB_BASE 0xFFE7040000UL
  254. #define DW_USB_SIZE 0x10000U
  255. #define DW_TIMER0_BASE 0xFFEFC32000UL
  256. #define DW_TIMER0_SIZE 0x14U
  257. #define DW_TIMER1_BASE (DW_TIMER0_BASE+DW_TIMER0_SIZE)
  258. #define DW_TIMER1_SIZE DW_TIMER0_SIZE
  259. #define DW_TIMER2_BASE 0xFFFFC33000UL
  260. #define DW_TIMER2_SIZE DW_TIMER1_SIZE
  261. #define DW_TIMER3_BASE (DW_TIMER2_BASE+DW_TIMER2_SIZE)
  262. #define DW_TIMER3_SIZE DW_TIMER2_SIZE
  263. #define DW_UART0_BASE 0xFFE7014000UL
  264. #define DW_UART0_SIZE 0x4000U
  265. #define DW_UART1_BASE 0xFFE7F00000UL
  266. #define DW_UART1_SIZE 0x4000U
  267. #define DW_UART2_BASE 0xFFEC010000UL
  268. #define DW_UART2_SIZE 0x4000U
  269. #define DW_UART3_BASE 0xFFE7F04000UL
  270. #define DW_UART3_SIZE 0x4000U
  271. #define DW_UART4_BASE 0xFFF7F08000UL
  272. #define DW_UART4_SIZE 0x4000U
  273. #define DW_UART5_BASE 0xFFF7F0C000UL
  274. #define DW_UART5_SIZE 0x4000U
  275. #define DW_GPIO0_BASE 0xFFEC005000UL
  276. #define DW_GPIO0_SIZE 0x1000U
  277. #define DW_GPIO1_BASE 0xFFEC006000UL
  278. #define DW_GPIO1_SIZE 0x1000U
  279. #define DW_GPIO2_BASE 0xFFE7F34000UL
  280. #define DW_GPIO2_SIZE 0x4000U
  281. #define DW_GPIO3_BASE 0xFFE7F38000UL
  282. #define DW_GPIO3_SIZE 0x4000U
  283. #define DW_WDT_BASE 0xFFEFC30000UL
  284. #define DW_WDT_BASE_SZIE 0x1000U
  285. #define DW_DMA_BASE 0xFFEFC00000UL
  286. #define DW_DMA_BASE_SZIE 0x4000U
  287. #define WJ_IOC_BASE1 0xFFEC007000UL
  288. #define WJ_IOC_SIZE 0x1000U
  289. #define WJ_IOC_BASE2 0xFFE7F3C000UL
  290. #define WJ_IOC_SIZE 0x1000U
  291. #define WJ_CPR_BASE 0xFFCB000000UL
  292. #define WJ_CPR_BASE_SIZE 0x1000000U
  293. #define DW_SPI0_BASE 0xFFF700C000UL
  294. #define DW_SPI0_BASE_SIZE 0x10000U
  295. #define DW_QSPI0_BASE 0xFFEA000000UL
  296. #define DW_QSPI0_BASE_SIZE 0x10000U
  297. #define DW_QSPI1_BASE 0xFFE8000000UL
  298. #define DW_QSPI1_BASE_SIZE 0x10000U
  299. #define DW_I2C0_BASE 0xFFE701C000UL
  300. #define DW_I2C0_BASE_SIZE 0x4000U
  301. #define DW_I2C1_BASE 0xFFE7F24000UL
  302. #define DW_I2C1_BASE_SIZE 0x4000U
  303. #define DW_I2C2_BASE 0xFFEC00C000UL
  304. #define DW_I2C2_BASE_SIZE 0x4000U
  305. #define DW_I2C3_BASE 0xFFFC010000UL
  306. #define DW_I2C3_BASE_SIZE 0x4000U
  307. #define DW_I2C4_BASE 0xFFE7F28000UL
  308. #define DW_I2C4_BASE_SIZE 0x4000U
  309. #define DW_I2C5_BASE 0xFFE7F2C000UL
  310. #define DW_I2C5_BASE_SIZE 0x4000U
  311. #define WJ_MBOX_BASE 0xFFFFC38000UL
  312. #define WJ_MBOX_SIZE 0x1000U
  313. #define WJ_MBOX1_BASE 0xFFFFC48000UL
  314. #define WJ_MBOX1_SIZE 0x1000U
  315. #define DW_EMMC_BASE 0xFFE7080000UL
  316. #define DW_EMMC_SIZE 0x1000U
  317. #define DW_SD_BASE 0xFFE7090000UL
  318. #define DW_SD_SIZE 0x1000U
  319. #define DCD_ISO7816_BASE 0xFFF7F30000ULL
  320. #define DCD_ISO7816_SIZE 0x4000UL
  321. #define RB_RNG_BASE 0xFFFF300000UL
  322. #define RB_RNG_SIZE 0x10000U
  323. #define RB_EIP150B_BASE 0xFFFF300000UL
  324. #define RB_EIP150B_SIZE 0x10000U
  325. #define RB_EIP28_BASE (RB_EIP150B_BASE + 0x4000)
  326. #define RB_EIP28_SIZE 0x3FFCU
  327. #define RB_EIP120SI_BASE 0xFFFF310000UL
  328. #define RB_EIP120SI_SIZE 0x10000U
  329. #define RB_EIP120SII_BASE 0xFFFF320000UL
  330. #define RB_EIP120SII_SIZE 0x10000U
  331. #define RB_EIP120SIII_BASE 0xFFFF330000UL
  332. #define RB_EIP120SIII_SIZE 0x10000U
  333. #define TEE_SYS_BASE 0xFFFF200000UL
  334. #define TEE_SYS_SIZE 0x10000U
  335. #define PLIC_BASE 0xFFD8000000ULL
  336. #define WJ_AON_SYSRST_GEN_BASE 0xFFFFF44000UL
  337. #define WJ_AON_SYSRST_GEN_SIZE 0x2000U
  338. #define KEYRAM_BASE 0xFFFF260000UL
  339. #define KEYRAM_SIZE 0x10000U
  340. #define TEE_SYS_BASE 0xFFFF200000UL
  341. #define TEE_SYS_SIZE 0x10000U
  342. #define TEE_SYS_EFUSE_LC_PRELD_OFF 0x64
  343. #define TEE_SYS_EFUSE_LC_READ_OFF 0x68
  344. #define TEE_SYS_EFUSE_DBG_KEY1_OFF 0x70
  345. #define IOPMP_EIP120I_BASE 0xFFFF220000UL
  346. #define IOPMP_EIP120I_SIZE 0x10000
  347. #define IOPMP_EIP120II_BASE 0xFFFF230000UL
  348. #define IOPMP_EIP120II_SIZE 0x10000
  349. #define IOPMP_EIP120III_BASE 0xFFFF240000UL
  350. #define IOPMP_EIP120III_SIZE 0x10000
  351. #define IOPMP_TEE_DMAC_BASE 0xFFFF250000UL
  352. #define IOPMP_TEE_DMAC_SIZE 0x10000
  353. #define IOPMP_EMMC_BASE 0xFFFC028000UL
  354. #define IOPMP_EMMC_SIZE 0x1000
  355. #define IOPMP_SDIO0_BASE 0xFFFC029000UL
  356. #define IOPMP_SDIO0_SIZE 0x1000
  357. #define IOPMP_SDIO1_BASE 0xFFFC02a000UL
  358. #define IOPMP_SDIO1_SIZE 0x1000
  359. #define CONFIG_MAILBOX_CHANNEL_NUM 4U
  360. #define CONFIG_RTC_FAMILY_D
  361. #define CONFIG_DW_AXI_DMA_8CH_NUM_CHANNELS
  362. #define SOC_OM_ADDRBASE 0xFFEF018010
  363. #define SOC_OSC_BOOT_ADDRBASE 0xFFEF010314
  364. #define SOC_INTERNAL_SRAM_BASEADDR 0xFFE0000000
  365. #define SOC_INTERNAL_SRAM_SIZE (1536 * 1024) //1.5MB
  366. #define SOC_BROM_BASE_ADDRESS 0xFFFFD00000
  367. #define CONFIG_OTP_BASE_ADDR 0 // FIXME:
  368. #define CONFIG_OTP_BANK_SIZE (8 * 1024)
  369. #define AO_SYS_REG_BASE 0xFFFFF48000UL
  370. #define AO_SYS_REG_SIZE 0x2000U
  371. #define SPIFLASH_BASE (0x18000000UL)
  372. #define bootsel() \
  373. ({ unsigned int __v = (*(volatile uint32_t *) (0xFFEF018010)); __v&0x7; })
  374. #define osc_bootsel() \
  375. ({ unsigned int __v = (*(volatile uint32_t *) (0xFFEF010314)); __v&0x1; })
  376. #define FULLMASK_APTEECLK_ADDRBASE 0xFFFF011000
  377. #define FULLMASK_TEE_PLL_CFG0_OFF 0x60
  378. #define FULLMASK_TEE_PLL_CFG1_OFF 0x64
  379. #define FULLMASK_TEE_PLL_CFG3_OFF 0x6c
  380. #define FULLMASK_PLL_STS_OFF 0x80
  381. #define FULLMASK_TEESYS_CLK_TEECFG_OFF 0x1cc
  382. #define FULLMASK_TEESYS_HCLK_SWITCH_SEL (0x2000U)
  383. #define FULLMASK_PLL_STS_TEE_PLL_LOCK (0x400U)
  384. #define FULLMASK_TEE_PLL_LOCK_TIMEOUT (0x3U) //unit: 10us
  385. #define FULLMASK_TEE_PLL_CFG3_CALLOCK_CNT_EN (0x400)
  386. #define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_PULSE (0x200)
  387. #define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_SWEN (0x100)
  388. #define FULLMASK_TEE_PLL_CFG3_DSKEWCAL_RDY (0x80)
  389. #define FULLMASK_TEE_PLL_DSKEWCAL_RDY_TIMEOUT (200U) //unit: 10us
  390. #define FULLMASK_TEE_PLL_CFG1_PWR_DOWN 0x21000000
  391. #define FULLMASK_TEE_PLL_CFG1_PWR_ON 0x01000000
  392. #define FULLMASK_TEE_PLL_CFG0_792M 0x01306301
  393. #define FULLMASK_AONSYSREG_ADDRBASE 0xFFFFF48000
  394. #define FULLMASK_AONSYSREG_PLL_DSKEW_LOCK_OFF 0x22c
  395. #define FULLMASK_AONSYSREG_PLL_DSKEW_BYPASS (0x2U)
  396. #define FULLMASK_AONSYSREG_RC_READY_OFF 0x7c
  397. #define FULLMASK_AONSYSREG_RC_READY (0x1U)
  398. #define FULLMASK_RC_READY_TIMEOUT (2U) //unit: 10us
  399. #define FULLMASK_AONSYSREG_RC_OFF 0x74
  400. #define FULLMASK_AONSYSREG_RC_VAL_POS 0
  401. #define FULLMASK_AONSYSREG_RC_VAL_MSK 0xFFF
  402. #ifdef __cplusplus
  403. }
  404. #endif
  405. #endif /* _SOC_H_ */